Skip to content

[ARM] Add missing earlyclobber to sqrshr and uqrshl instructions. #77782

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Jan 16, 2024
Merged

[ARM] Add missing earlyclobber to sqrshr and uqrshl instructions. #77782

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
60f7222
[Aarch64] Add missing earlyclobber to sqrshr and uqrshl instructions.
AlfieRichardsArm Jan 10, 2024
42889a0
Move sqrshr-uqrshl-unpredictable.ll test to llvm/test/CodeGen/ARM
AlfieRichardsArm Jan 11, 2024
ba64be9
Move llvm/test/MC/AArch64/mve-sqrshr-uqrshl-earlyclobber.s to llvm/te…
AlfieRichardsArm Jan 11, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMInstrMVE.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -478,7 +478,7 @@ def MVE_URSHR : MVE_ScalarShiftSRegImm<"urshr", 0b01>;

class MVE_ScalarShiftSRegReg<string iname, bits<2> op5_4>
: MVE_ScalarShiftSingleReg<iname, (ins rGPR:$RdaSrc, rGPR:$Rm),
"$RdaSrc, $Rm", "$RdaDest = $RdaSrc",
"$RdaSrc, $Rm", "@earlyclobber $RdaDest,$RdaDest = $RdaSrc",
[(set rGPR:$RdaDest,
(i32 (!cast<Intrinsic>("int_arm_mve_" # iname)
(i32 rGPR:$RdaSrc), (i32 rGPR:$Rm))))]> {
Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8308,6 +8308,14 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
break;
}
case ARM::MVE_SQRSHR:
case ARM::MVE_UQRSHL: {
if (Operands[2]->getReg() == Operands[3]->getReg()) {
return Error(Operands[2]->getStartLoc(),
"Rda register and Rm register can't be identical");
}
break;
}
case ARM::UMAAL:
case ARM::UMLAL:
case ARM::UMULL:
Expand Down
21 changes: 21 additions & 0 deletions llvm/test/CodeGen/ARM/sqrshr-uqrshl-unpredictable.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
; RUN: llc -mtriple armv8.1m.main -mattr=+mve %s -o - | FileCheck %s

; Check that we don't create an unpredictable sqrshr or uqrshl instruction,
; e.g. sqrshr r0, r0

declare i32 @llvm.arm.mve.sqrshr(i32, i32) #1
declare i32 @llvm.arm.mve.uqrshl(i32, i32) #1

define i32 @sqrshr() #0 {
; CHECK-LABEL: sqrshr
; CHECK-NOT: sqrshr r[[REG:[0-9]+]], r[[REG]]
%1 = tail call i32 @llvm.arm.mve.sqrshr(i32 1, i32 1)
ret i32 %1
}

define i32 @uqrshl() #0 {
; CHECK-LABEL: uqrshl
; CHECK-NOT: uqrshl r[[REG:[0-9]+]], r[[REG]]
%1 = tail call i32 @llvm.arm.mve.uqrshl(i32 1, i32 1)
ret i32 %1
}
6 changes: 6 additions & 0 deletions llvm/test/MC/ARM/mve-sqrshr-uqrshl-earlyclobber.s
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,6 @@
@ RUN: not llvm-mc -triple armv8.1m.main -mattr=+mve < %s 2>&1 | FileCheck %s

sqrshr r1, r1
@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Rda register and Rm register can't be identical
uqrshl r1, r1
@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Rda register and Rm register can't be identical