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[AMDGPU] SILowerSGPRSpills: do not update MRI reserve registers #77888

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Merged
merged 1 commit into from
Jan 23, 2024
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[AMDGPU] SILowerSGPRSpills: do not update MRI reserve registers #77888

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9 changes: 0 additions & 9 deletions llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -332,7 +332,6 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
}

bool MadeChange = false;
bool NewReservedRegs = false;
bool SpilledToVirtVGPRLanes = false;

// TODO: CSR VGPRs will never be spilled to AGPRs. These can probably be
Expand Down Expand Up @@ -370,7 +369,6 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
// intermediate spills is implemented. There is no such support
// currently exist in the LLVM compiler.
if (FuncInfo->allocateSGPRSpillToVGPRLane(MF, FI, true)) {
NewReservedRegs = true;
bool Spilled = TRI->eliminateSGPRToVGPRSpillFrameIndex(
MI, FI, nullptr, Indexes, LIS, true);
if (!Spilled)
Expand Down Expand Up @@ -442,12 +440,5 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
SaveBlocks.clear();
RestoreBlocks.clear();

// Updated the reserved registers with any physical VGPRs added for SGPR
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@cdevadas cdevadas Jan 16, 2024 •
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The phys VGPRs used for CSR SGPR spilling shouldn't be reused during SIPreAllocateWWMRegs.
I hope they will be marked reserved while getting the AllocationOrder from RegClassInfo.runOnMachineFunction(MF).
@arsenm any specific reason they are marked Reserved here explicitly?

// spills.
if (NewReservedRegs) {
for (Register Reg : FuncInfo->getWWMReservedRegs())
MRI.reserveReg(Reg, TRI);
}

return MadeChange;
}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
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@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=amdgcn-unknown-amdpal -mcpu=gfx1030 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs --stress-regalloc=2 -o - %s | FileCheck -check-prefix GCN %s
# RUN: llc -mtriple=amdgcn-unknown-amdpal -mcpu=gfx1030 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs --stress-regalloc=5 -o - %s | FileCheck -check-prefix GCN %s
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To explain this test change:
--stress-regalloc=2 limits the VGPR class to 2 registers after reserve registers are subtracted.
Without reservation by SILowerSGPRSpills the 3 VGPRs count against the VGPR class usage, so the class size must be enlarged (to 5) to accommodate them.

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To preempt an obvious follow up question: "how does SILowerSGPRSpill exceed the register limit?"
allocateSGPRSpillToVGPRLane uses findUnusedRegister which does not consult the allocation in RegisterClassInfo which imposes the limit.

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This option should have been better integrated into MRI to fully limit the register usage in various other passes.


--- |
define amdgpu_gfx [13 x i32] @test_main() #0 {
Expand Down