Skip to content

[AMDGPU] Sign extend simm16 in setreg intrinsic #77997

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Jan 16, 2024
+70 −7
Merged

[AMDGPU] Sign extend simm16 in setreg intrinsic #77997

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
01af6c9
[AMDGPU] Sign extend simm16 in setreg intrinsic
rampitec Jan 12, 2024
daeef9d
Switch to use of TImmLeaf with SDNodeXForm
rampitec Jan 15, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
11 changes: 6 additions & 5 deletions llvm/lib/Target/AMDGPU/SOPInstructions.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1117,14 +1117,12 @@ def S_GETREG_B32 : SOPK_Pseudo <
let Defs = [MODE], Uses = [MODE] in {

// FIXME: Need to truncate immediate to 16-bits.
class S_SETREG_B32_Pseudo <list<dag> pattern=[]> : SOPK_Pseudo <
class S_SETREG_B32_Pseudo : SOPK_Pseudo <
"s_setreg_b32",
(outs), (ins SReg_32:$sdst, hwreg:$simm16),
"$simm16, $sdst",
pattern>;
"$simm16, $sdst">;

def S_SETREG_B32 : S_SETREG_B32_Pseudo <
[(int_amdgcn_s_setreg (i32 timm:$simm16), i32:$sdst)]> {
def S_SETREG_B32 : S_SETREG_B32_Pseudo {
// Use custom inserter to optimize some cases to
// S_DENORM_MODE/S_ROUND_MODE/S_SETREG_B32_mode.
let usesCustomInserter = 1;
Expand Down Expand Up @@ -1160,6 +1158,9 @@ def S_SETREG_IMM32_B32_mode : S_SETREG_IMM32_B32_Pseudo {

} // End Defs = [MODE], Uses = [MODE]

def : GCNPat<(int_amdgcn_s_setreg (i32 timm:$simm16), i32:$sdst),
(S_SETREG_B32 $sdst, (as_i16timm $simm16))>;

class SOPK_WAITCNT<string opName, list<dag> pat=[]> :
SOPK_Pseudo<
opName,
Expand Down
66 changes: 66 additions & 0 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1433,6 +1433,72 @@ define amdgpu_kernel void @test_setreg_set_4_bits_straddles_round_and_denorm() {
ret void
}

define amdgpu_ps void @test_63489(i32 inreg %var.mode) {
; GFX6-LABEL: test_63489:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9]
; GFX6-NEXT: ;;#ASMSTART
; GFX6-NEXT: ;;#ASMEND
; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
;
; GFX789-LABEL: test_63489:
; GFX789: ; %bb.0:
; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9]
; GFX789-NEXT: ;;#ASMSTART
; GFX789-NEXT: ;;#ASMEND
; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
;
; GFX10-LABEL: test_63489:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9]
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
;
; GFX11-LABEL: test_63489:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9]
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
call void @llvm.amdgcn.s.setreg(i32 63489, i32 %var.mode)
call void asm sideeffect "", ""()
ret void
}

define amdgpu_ps void @test_minus_2047(i32 inreg %var.mode) {
; GFX6-LABEL: test_minus_2047:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9]
; GFX6-NEXT: ;;#ASMSTART
; GFX6-NEXT: ;;#ASMEND
; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
;
; GFX789-LABEL: test_minus_2047:
; GFX789: ; %bb.0:
; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9]
; GFX789-NEXT: ;;#ASMSTART
; GFX789-NEXT: ;;#ASMEND
; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
;
; GFX10-LABEL: test_minus_2047:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9]
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
;
; GFX11-LABEL: test_minus_2047:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9]
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
call void @llvm.amdgcn.s.setreg(i32 -2047, i32 %var.mode)
call void asm sideeffect "", ""()
ret void
}

; FIXME: Broken for DAG
; define void @test_setreg_roundingmode_var_vgpr(i32 %var.mode) {
; call void @llvm.amdgcn.s.setreg(i32 4097, i32 %var.mode)
Expand Down