Skip to content

[RISCV] Add IntrArgMemOnly for vector load/store intrinsic #78415

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jan 23, 2024
Merged

[RISCV] Add IntrArgMemOnly for vector load/store intrinsic #78415

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
29 changes: 19 additions & 10 deletions llvm/include/llvm/IR/IntrinsicsRISCV.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -147,15 +147,17 @@ let TargetPrefix = "riscv" in {
class RISCVUSMLoad
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[llvm_ptr_ty, llvm_anyint_ty],
[NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic {
[NoCapture<ArgIndex<0>>, IntrReadMem, IntrArgMemOnly]>,
RISCVVIntrinsic {
let VLOperand = 1;
}
// For unit stride load
// Input: (passthru, pointer, vl)
class RISCVUSLoad
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_ptr_ty, llvm_anyint_ty],
[NoCapture<ArgIndex<1>>, IntrReadMem]>, RISCVVIntrinsic {
[NoCapture<ArgIndex<1>>, IntrReadMem, IntrArgMemOnly]>,
RISCVVIntrinsic {
let VLOperand = 2;
}
// For unit stride fault-only-first load
Expand All @@ -177,7 +179,8 @@ let TargetPrefix = "riscv" in {
[LLVMMatchType<0>, llvm_ptr_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<1>],
[NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<4>>, IntrReadMem]>,
[NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<4>>, IntrReadMem,
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

fault-only-first load may write vl, is this still IntrArgMemOnly?

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I presume no, from the definition of IntrArgMemOnly in Intrinsics.td:

Other than reads from and (possibly volatile) writes to memory, it has no side effects.

Copy link
Collaborator

@topperc topperc Jan 17, 2024 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This class isn't used for fault-only-first loads. That's RISCVUSLoadFF and RISCVUSLoadFFMasked. This patch isn't touching those intrinsics.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Oh I misread it, I was reading the line below.

IntrArgMemOnly]>,
RISCVVIntrinsic {
let VLOperand = 3;
}
Expand Down Expand Up @@ -239,7 +242,8 @@ let TargetPrefix = "riscv" in {
class RISCVUSStore
: DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty, llvm_ptr_ty, llvm_anyint_ty],
[NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic {
[NoCapture<ArgIndex<1>>, IntrWriteMem, IntrArgMemOnly]>,
RISCVVIntrinsic {
let VLOperand = 2;
}
// For unit stride store with mask
Expand All @@ -249,7 +253,8 @@ let TargetPrefix = "riscv" in {
[llvm_anyvector_ty, llvm_ptr_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty],
[NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic {
[NoCapture<ArgIndex<1>>, IntrWriteMem, IntrArgMemOnly]>,
RISCVVIntrinsic {
let VLOperand = 3;
}
// For strided store
Expand Down Expand Up @@ -992,7 +997,8 @@ let TargetPrefix = "riscv" in {
!add(nf, -1))),
!listconcat(!listsplat(LLVMMatchType<0>, nf),
[llvm_ptr_ty, llvm_anyint_ty]),
[NoCapture<ArgIndex<nf>>, IntrReadMem]>, RISCVVIntrinsic {
[NoCapture<ArgIndex<nf>>, IntrReadMem, IntrArgMemOnly]>,
RISCVVIntrinsic {
let VLOperand = !add(nf, 1);
}
// For unit stride segment load with mask
Expand All @@ -1004,8 +1010,9 @@ let TargetPrefix = "riscv" in {
[llvm_ptr_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<1>]),
[ImmArg<ArgIndex<!add(nf, 3)>>, NoCapture<ArgIndex<nf>>, IntrReadMem]>,
RISCVVIntrinsic {
[ImmArg<ArgIndex<!add(nf, 3)>>, NoCapture<ArgIndex<nf>>,
IntrReadMem, IntrArgMemOnly]>,
RISCVVIntrinsic {
let VLOperand = !add(nf, 2);
}

Expand Down Expand Up @@ -1096,7 +1103,8 @@ let TargetPrefix = "riscv" in {
!listconcat([llvm_anyvector_ty],
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
[llvm_ptr_ty, llvm_anyint_ty]),
[NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {
[NoCapture<ArgIndex<nf>>, IntrWriteMem, IntrArgMemOnly]>,
RISCVVIntrinsic {
let VLOperand = !add(nf, 1);
}
// For unit stride segment store with mask
Expand All @@ -1108,7 +1116,8 @@ let TargetPrefix = "riscv" in {
[llvm_ptr_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty]),
[NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic {
[NoCapture<ArgIndex<nf>>, IntrWriteMem, IntrArgMemOnly]>,
RISCVVIntrinsic {
let VLOperand = !add(nf, 2);
}

Expand Down