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[AMDGPU] Fix predicates for BUFFER_ATOMIC_CSUB pattern #78701

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Merged
merged 1 commit into from
Jan 19, 2024
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[AMDGPU] Fix predicates for BUFFER_ATOMIC_CSUB pattern #78701

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/BUFInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1712,7 +1712,7 @@ defm : SIBufferAtomicPat<"SIbuffer_atomic_xor", i64, "BUFFER_ATOMIC_XOR_X2">;
defm : SIBufferAtomicPat<"SIbuffer_atomic_inc", i64, "BUFFER_ATOMIC_INC_X2">;
defm : SIBufferAtomicPat<"SIbuffer_atomic_dec", i64, "BUFFER_ATOMIC_DEC_X2">;

let SubtargetPredicate = HasAtomicCSubNoRtnInsts in
let OtherPredicates = [HasAtomicCSubNoRtnInsts] in
defm : SIBufferAtomicPat<"SIbuffer_atomic_csub", i32, "BUFFER_ATOMIC_CSUB", ["noret"]>;

let SubtargetPredicate = isGFX12Plus in {
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.csub.ll
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Expand Up @@ -16,7 +16,7 @@ main_body:

; GCN-LABEL: {{^}}buffer_atomic_csub_no_rtn:
; PREGFX12: buffer_atomic_csub v0, v1, s[0:3], 0 idxen
; GFX12PLUS: buffer_atomic_csub_u32 v0, v1, s[0:3], null idxen
; GFX12PLUS: buffer_atomic_sub_clamp_u32 v0, v1, s[0:3], null idxen
define amdgpu_ps void @buffer_atomic_csub_no_rtn(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex) #0 {
main_body:
%ret = call i32 @llvm.amdgcn.buffer.atomic.csub(i32 %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
Expand All @@ -34,7 +34,7 @@ main_body:

; GCN-LABEL: {{^}}buffer_atomic_csub_off4_slc_no_rtn:
; PREGFX12: buffer_atomic_csub v0, v1, s[0:3], 0 idxen offset:4 slc
; GFX12PLUS: buffer_atomic_csub_u32 v0, v1, s[0:3], null idxen offset:4 th:TH_ATOMIC_NT
; GFX12PLUS: buffer_atomic_sub_clamp_u32 v0, v1, s[0:3], null idxen offset:4 th:TH_ATOMIC_NT
define amdgpu_ps void @buffer_atomic_csub_off4_slc_no_rtn(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex) #0 {
main_body:
%ret = call i32 @llvm.amdgcn.buffer.atomic.csub(i32 %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i1 1)
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