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[AMDGPU] Update isLegalAddressingMode for GFX12 SMEM loads #78728

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Merged
merged 1 commit into from
Jan 24, 2024
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[AMDGPU] Update isLegalAddressingMode for GFX12 SMEM loads #78728

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15 changes: 8 additions & 7 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1525,13 +1525,14 @@ bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
if (AM.BaseOffs % 4 != 0)
return isLegalMUBUFAddressingMode(AM);

// There are no SMRD extloads, so if we have to do a small type access we
// will use a MUBUF load.
// FIXME?: We also need to do this if unaligned, but we don't know the
// alignment here.
// TODO: Update this for GFX12 which does have scalar sub-dword loads.
if (Ty->isSized() && DL.getTypeStoreSize(Ty) < 4)
return isLegalGlobalAddressingMode(AM);
if (!Subtarget->hasScalarSubwordLoads()) {
// There are no SMRD extloads, so if we have to do a small type access we
// will use a MUBUF load.
// FIXME?: We also need to do this if unaligned, but we don't know the
// alignment here.
if (Ty->isSized() && DL.getTypeStoreSize(Ty) < 4)
return isLegalGlobalAddressingMode(AM);
}

if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
// SMRD instructions have an 8-bit, dword offset on SI.
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