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[RISCV] Merge ADDI with X0 into base offset #78940

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Merged
merged 3 commits into from
Jan 23, 2024
Merged

[RISCV] Merge ADDI with X0 into base offset #78940

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9386574
[RISCV] Merge ADDI with X0 into base offset
tclin914 Jan 22, 2024
35104ab
Remove unnecessary the else.
tclin914 Jan 22, 2024
33c33c4
Remove new variable `Offset`
tclin914 Jan 22, 2024
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13 changes: 10 additions & 3 deletions llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -193,9 +193,16 @@ bool RISCVMergeBaseOffsetOpt::foldLargeOffset(MachineInstr &Hi,
if (AddiImmOp.getTargetFlags() != RISCVII::MO_None)
return false;
Register AddiReg = OffsetTail.getOperand(1).getReg();
if (!AddiReg.isVirtual())
return false;
int64_t OffLo = AddiImmOp.getImm();

// Handle rs1 of ADDI is X0.
if (AddiReg == RISCV::X0) {
LLVM_DEBUG(dbgs() << " Offset Instrs: " << OffsetTail);
foldOffset(Hi, Lo, TailAdd, OffLo);
OffsetTail.eraseFromParent();
return true;
}

MachineInstr &OffsetLui = *MRI->getVRegDef(AddiReg);
MachineOperand &LuiImmOp = OffsetLui.getOperand(1);
if (OffsetLui.getOpcode() != RISCV::LUI ||
Expand All @@ -206,7 +213,7 @@ bool RISCVMergeBaseOffsetOpt::foldLargeOffset(MachineInstr &Hi,
Offset += OffLo;
// RV32 ignores the upper 32 bits. ADDIW sign extends the result.
if (!ST->is64Bit() || OffsetTail.getOpcode() == RISCV::ADDIW)
Offset = SignExtend64<32>(Offset);
Offset = SignExtend64<32>(Offset);
// We can only fold simm32 offsets.
if (!isInt<32>(Offset))
return false;
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28 changes: 8 additions & 20 deletions llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
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Expand Up @@ -971,49 +971,37 @@ declare void @f(ptr)
define i32 @crash() {
; RV32I-LABEL: crash:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: lui a1, %hi(g)
; RV32I-NEXT: addi a1, a1, %lo(g)
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: lbu a0, 400(a0)
; RV32I-NEXT: lui a0, %hi(g+401)
; RV32I-NEXT: lbu a0, %lo(g+401)(a0)
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: sw a0, 0(zero)
; RV32I-NEXT: li a0, 0
; RV32I-NEXT: ret
;
; RV32I-MEDIUM-LABEL: crash:
; RV32I-MEDIUM: # %bb.0: # %entry
; RV32I-MEDIUM-NEXT: li a0, 1
; RV32I-MEDIUM-NEXT: .Lpcrel_hi14:
; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(g)
; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi14)
; RV32I-MEDIUM-NEXT: add a0, a1, a0
; RV32I-MEDIUM-NEXT: lbu a0, 400(a0)
; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g+401)
; RV32I-MEDIUM-NEXT: lbu a0, %pcrel_lo(.Lpcrel_hi14)(a0)
; RV32I-MEDIUM-NEXT: seqz a0, a0
; RV32I-MEDIUM-NEXT: sw a0, 0(zero)
; RV32I-MEDIUM-NEXT: li a0, 0
; RV32I-MEDIUM-NEXT: ret
;
; RV64I-LABEL: crash:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: lui a1, %hi(g)
; RV64I-NEXT: addi a1, a1, %lo(g)
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lbu a0, 400(a0)
; RV64I-NEXT: lui a0, %hi(g+401)
; RV64I-NEXT: lbu a0, %lo(g+401)(a0)
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: sw a0, 0(zero)
; RV64I-NEXT: li a0, 0
; RV64I-NEXT: ret
;
; RV64I-MEDIUM-LABEL: crash:
; RV64I-MEDIUM: # %bb.0: # %entry
; RV64I-MEDIUM-NEXT: li a0, 1
; RV64I-MEDIUM-NEXT: .Lpcrel_hi14:
; RV64I-MEDIUM-NEXT: auipc a1, %pcrel_hi(g)
; RV64I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi14)
; RV64I-MEDIUM-NEXT: add a0, a1, a0
; RV64I-MEDIUM-NEXT: lbu a0, 400(a0)
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g+401)
; RV64I-MEDIUM-NEXT: lbu a0, %pcrel_lo(.Lpcrel_hi14)(a0)
; RV64I-MEDIUM-NEXT: seqz a0, a0
; RV64I-MEDIUM-NEXT: sw a0, 0(zero)
; RV64I-MEDIUM-NEXT: li a0, 0
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