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[AMDGPU] Don't fix the scavenge slot at offset 0 #79136

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Merged
merged 4 commits into from
Feb 9, 2024
Merged

[AMDGPU] Don't fix the scavenge slot at offset 0 #79136

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cdbfc1d
[AMDGPU] Offset can be 0 in eliminateFrameIndex
rovka Sep 22, 2023
85f5f8d
[AMDGPU] Don't fix the scavenge slot at offset 0
rovka Jan 19, 2024
b15ac2b
Non-trivial tests
rovka Jan 22, 2024
1087754
Undelete testcase
rovka Jan 24, 2024
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12 changes: 4 additions & 8 deletions llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -520,14 +520,10 @@ int SIMachineFunctionInfo::getScavengeFI(MachineFrameInfo &MFI,
const SIRegisterInfo &TRI) {
if (ScavengeFI)
return *ScavengeFI;
if (isBottomOfStack()) {
ScavengeFI = MFI.CreateFixedObject(
TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
} else {
ScavengeFI = MFI.CreateStackObject(
TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
}

ScavengeFI =
MFI.CreateStackObject(TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
return *ScavengeFI;
}

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3 changes: 0 additions & 3 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2273,9 +2273,6 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
if (FrameReg)
FIOp.ChangeToRegister(FrameReg, false);

if (!Offset)
return false;

MachineOperand *OffsetOp =
TII->getNamedOperand(*MI, AMDGPU::OpName::offset);
int64_t NewOffset = Offset + OffsetOp->getImm();
Expand Down
54 changes: 27 additions & 27 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,8 @@ define amdgpu_kernel void @kernel_caller_byval() {
; MUBUF-NEXT: s_add_u32 s0, s0, s7
; MUBUF-NEXT: s_addc_u32 s1, s1, 0
; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:12
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:16
Expand Down Expand Up @@ -95,25 +97,23 @@ define amdgpu_kernel void @kernel_caller_byval() {
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:116
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:120
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:124
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:132
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0
; MUBUF-NEXT: s_nop 0
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:12
; MUBUF-NEXT: buffer_load_dword v2, off, s[0:3], 0 offset:16
; MUBUF-NEXT: buffer_load_dword v3, off, s[0:3], 0 offset:20
; MUBUF-NEXT: buffer_load_dword v4, off, s[0:3], 0 offset:24
; MUBUF-NEXT: buffer_load_dword v5, off, s[0:3], 0 offset:28
; MUBUF-NEXT: buffer_load_dword v6, off, s[0:3], 0 offset:32
; MUBUF-NEXT: buffer_load_dword v7, off, s[0:3], 0 offset:36
; MUBUF-NEXT: buffer_load_dword v8, off, s[0:3], 0 offset:40
; MUBUF-NEXT: buffer_load_dword v9, off, s[0:3], 0 offset:44
; MUBUF-NEXT: buffer_load_dword v10, off, s[0:3], 0 offset:48
; MUBUF-NEXT: buffer_load_dword v11, off, s[0:3], 0 offset:52
; MUBUF-NEXT: buffer_load_dword v12, off, s[0:3], 0 offset:56
; MUBUF-NEXT: buffer_load_dword v13, off, s[0:3], 0 offset:60
; MUBUF-NEXT: buffer_load_dword v14, off, s[0:3], 0 offset:64
; MUBUF-NEXT: buffer_load_dword v15, off, s[0:3], 0 offset:68
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:4
; MUBUF-NEXT: buffer_load_dword v2, off, s[0:3], 0 offset:8
; MUBUF-NEXT: buffer_load_dword v3, off, s[0:3], 0 offset:12
; MUBUF-NEXT: buffer_load_dword v4, off, s[0:3], 0 offset:16
; MUBUF-NEXT: buffer_load_dword v5, off, s[0:3], 0 offset:20
; MUBUF-NEXT: buffer_load_dword v6, off, s[0:3], 0 offset:24
; MUBUF-NEXT: buffer_load_dword v7, off, s[0:3], 0 offset:28
; MUBUF-NEXT: buffer_load_dword v8, off, s[0:3], 0 offset:32
; MUBUF-NEXT: buffer_load_dword v9, off, s[0:3], 0 offset:36
; MUBUF-NEXT: buffer_load_dword v10, off, s[0:3], 0 offset:40
; MUBUF-NEXT: buffer_load_dword v11, off, s[0:3], 0 offset:44
; MUBUF-NEXT: buffer_load_dword v12, off, s[0:3], 0 offset:48
; MUBUF-NEXT: buffer_load_dword v13, off, s[0:3], 0 offset:52
; MUBUF-NEXT: buffer_load_dword v14, off, s[0:3], 0 offset:56
; MUBUF-NEXT: buffer_load_dword v15, off, s[0:3], 0 offset:60
; MUBUF-NEXT: s_movk_i32 s32, 0x1400
; MUBUF-NEXT: s_getpc_b64 s[4:5]
; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_byval@rel32@lo+4
Expand Down Expand Up @@ -160,6 +160,7 @@ define amdgpu_kernel void @kernel_caller_byval() {
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; FLATSCR-NEXT: v_mov_b32_e32 v1, 0
; FLATSCR-NEXT: s_mov_b32 s0, 0
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s0
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s0 offset:8
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s0 offset:16
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s0 offset:24
Expand All @@ -175,16 +176,15 @@ define amdgpu_kernel void @kernel_caller_byval() {
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s0 offset:104
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s0 offset:112
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s0 offset:120
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s0 offset:128
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s0 offset:8
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s0
; FLATSCR-NEXT: s_nop 0
; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s0 offset:16
; FLATSCR-NEXT: scratch_load_dwordx2 v[4:5], off, s0 offset:24
; FLATSCR-NEXT: scratch_load_dwordx2 v[6:7], off, s0 offset:32
; FLATSCR-NEXT: scratch_load_dwordx2 v[8:9], off, s0 offset:40
; FLATSCR-NEXT: scratch_load_dwordx2 v[10:11], off, s0 offset:48
; FLATSCR-NEXT: scratch_load_dwordx2 v[12:13], off, s0 offset:56
; FLATSCR-NEXT: scratch_load_dwordx2 v[14:15], off, s0 offset:64
; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s0 offset:8
; FLATSCR-NEXT: scratch_load_dwordx2 v[4:5], off, s0 offset:16
; FLATSCR-NEXT: scratch_load_dwordx2 v[6:7], off, s0 offset:24
; FLATSCR-NEXT: scratch_load_dwordx2 v[8:9], off, s0 offset:32
; FLATSCR-NEXT: scratch_load_dwordx2 v[10:11], off, s0 offset:40
; FLATSCR-NEXT: scratch_load_dwordx2 v[12:13], off, s0 offset:48
; FLATSCR-NEXT: scratch_load_dwordx2 v[14:15], off, s0 offset:56
; FLATSCR-NEXT: s_movk_i32 s32, 0x50
; FLATSCR-NEXT: s_getpc_b64 s[0:1]
; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_byval@rel32@lo+4
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
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Expand Up @@ -12,10 +12,10 @@ define amdgpu_kernel void @stack_write_fi() {
; CHECK-NEXT: s_mov_b32 s5, 0
; CHECK-NEXT: s_mov_b32 s4, 0
; CHECK-NEXT: v_mov_b32_e32 v0, s5
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], 0
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_endpgm
entry:
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
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Expand Up @@ -12,7 +12,7 @@ define amdgpu_ps void @amdgpu_ps() {
; MESA-NEXT: s_add_u32 flat_scratch_lo, s2, s4
; MESA-NEXT: s_mov_b64 s[0:1], src_private_base
; MESA-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; MESA-NEXT: v_mov_b32_e32 v0, 4
; MESA-NEXT: v_mov_b32_e32 v0, 0
; MESA-NEXT: v_mov_b32_e32 v1, s1
; MESA-NEXT: v_mov_b32_e32 v2, 0
; MESA-NEXT: flat_store_dword v[0:1], v2
Expand All @@ -24,7 +24,7 @@ define amdgpu_ps void @amdgpu_ps() {
; PAL-NEXT: s_getpc_b64 s[2:3]
; PAL-NEXT: s_mov_b32 s2, s0
; PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; PAL-NEXT: v_mov_b32_e32 v0, 4
; PAL-NEXT: v_mov_b32_e32 v0, 0
; PAL-NEXT: v_mov_b32_e32 v2, 0
; PAL-NEXT: s_waitcnt lgkmcnt(0)
; PAL-NEXT: s_and_b32 s3, s3, 0xffff
Expand Down
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