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[RISCV] Move exact VLEN VLMAX encoding to RISCVInsertVSETVLI. NFC-ish #79338

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[RISCV] Move exact VLEN VLMAX encoding to RISCVInsertVSETVLI. NFC-ish #79338

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33 changes: 10 additions & 23 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2640,16 +2640,8 @@ static SDValue getAllOnesMask(MVT VecVT, SDValue VL, const SDLoc &DL,
return DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL);
}

static SDValue getVLOp(uint64_t NumElts, MVT ContainerVT, const SDLoc &DL,
SelectionDAG &DAG, const RISCVSubtarget &Subtarget) {
// If we know the exact VLEN, and our VL is exactly equal to VLMAX,
// canonicalize the representation. InsertVSETVLI will pick the immediate
// encoding later if profitable.
const auto [MinVLMAX, MaxVLMAX] =
RISCVTargetLowering::computeVLMAXBounds(ContainerVT, Subtarget);
if (MinVLMAX == MaxVLMAX && NumElts == MinVLMAX)
return DAG.getRegister(RISCV::X0, Subtarget.getXLenVT());

static SDValue getVLOp(uint64_t NumElts, const SDLoc &DL, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
return DAG.getConstant(NumElts, DL, Subtarget.getXLenVT());
}

Expand All @@ -2666,7 +2658,7 @@ static std::pair<SDValue, SDValue>
getDefaultVLOps(uint64_t NumElts, MVT ContainerVT, const SDLoc &DL,
SelectionDAG &DAG, const RISCVSubtarget &Subtarget) {
assert(ContainerVT.isScalableVector() && "Expecting scalable container type");
SDValue VL = getVLOp(NumElts, ContainerVT, DL, DAG, Subtarget);
SDValue VL = getVLOp(NumElts, DL, DAG, Subtarget);
SDValue Mask = getAllOnesMask(ContainerVT, VL, DL, DAG);
return {Mask, VL};
}
Expand Down Expand Up @@ -9087,8 +9079,7 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
MVT VT = Op->getSimpleValueType(0);
MVT ContainerVT = getContainerForFixedLengthVector(VT);

SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG,
Subtarget);
SDValue VL = getVLOp(VT.getVectorNumElements(), DL, DAG, Subtarget);
SDValue IntID = DAG.getTargetConstant(VlsegInts[NF - 2], DL, XLenVT);
auto *Load = cast<MemIntrinsicSDNode>(Op);
SmallVector<EVT, 9> ContainerVTs(NF, ContainerVT);
Expand Down Expand Up @@ -9208,8 +9199,7 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
MVT VT = Op->getOperand(2).getSimpleValueType();
MVT ContainerVT = getContainerForFixedLengthVector(VT);

SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG,
Subtarget);
SDValue VL = getVLOp(VT.getVectorNumElements(), DL, DAG, Subtarget);
SDValue IntID = DAG.getTargetConstant(VssegInts[NF - 2], DL, XLenVT);
SDValue Ptr = Op->getOperand(NF + 2);

Expand Down Expand Up @@ -9625,7 +9615,7 @@ SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
// Set the vector length to only the number of elements we care about. Note
// that for slideup this includes the offset.
unsigned EndIndex = OrigIdx + SubVecVT.getVectorNumElements();
SDValue VL = getVLOp(EndIndex, ContainerVT, DL, DAG, Subtarget);
SDValue VL = getVLOp(EndIndex, DL, DAG, Subtarget);

// Use tail agnostic policy if we're inserting over Vec's tail.
unsigned Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED;
Expand Down Expand Up @@ -9805,8 +9795,7 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget).first;
// Set the vector length to only the number of elements we care about. This
// avoids sliding down elements we're going to discard straight away.
SDValue VL = getVLOp(SubVecVT.getVectorNumElements(), ContainerVT, DL, DAG,
Subtarget);
SDValue VL = getVLOp(SubVecVT.getVectorNumElements(), DL, DAG, Subtarget);
SDValue SlidedownAmt = DAG.getConstant(OrigIdx, DL, XLenVT);
SDValue Slidedown =
getVSlidedown(DAG, Subtarget, DL, ContainerVT,
Expand Down Expand Up @@ -9881,8 +9870,7 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
SDValue SlidedownAmt = DAG.getElementCount(DL, XLenVT, RemIdx);
auto [Mask, VL] = getDefaultScalableVLOps(InterSubVT, DL, DAG, Subtarget);
if (SubVecVT.isFixedLengthVector())
VL = getVLOp(SubVecVT.getVectorNumElements(), InterSubVT, DL, DAG,
Subtarget);
VL = getVLOp(SubVecVT.getVectorNumElements(), DL, DAG, Subtarget);
SDValue Slidedown =
getVSlidedown(DAG, Subtarget, DL, InterSubVT, DAG.getUNDEF(InterSubVT),
Vec, SlidedownAmt, Mask, VL);
Expand Down Expand Up @@ -10261,7 +10249,7 @@ RISCVTargetLowering::lowerFixedLengthVectorLoadToRVV(SDValue Op,
return DAG.getMergeValues({Result, NewLoad.getValue(1)}, DL);
}

SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG, Subtarget);
SDValue VL = getVLOp(VT.getVectorNumElements(), DL, DAG, Subtarget);

bool IsMaskOp = VT.getVectorElementType() == MVT::i1;
SDValue IntID = DAG.getTargetConstant(
Expand Down Expand Up @@ -10318,8 +10306,7 @@ RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,
return DAG.getStore(Store->getChain(), DL, NewValue, Store->getBasePtr(),
Store->getMemOperand());

SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG,
Subtarget);
SDValue VL = getVLOp(VT.getVectorNumElements(), DL, DAG, Subtarget);

bool IsMaskOp = VT.getVectorElementType() == MVT::i1;
SDValue IntID = DAG.getTargetConstant(
Expand Down
16 changes: 14 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -858,13 +858,14 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,

if (RISCVII::hasVLOp(TSFlags)) {
const MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));
const unsigned VLMAX = computeVLMAX(ST.getRealMaxVLen(), SEW, VLMul);

if (VLOp.isImm()) {
int64_t Imm = VLOp.getImm();
// Conver the VLMax sentintel to X0 register.
if (Imm == RISCV::VLMaxSentinel) {
// If we know the exact VLEN, see if we can use the constant encoding
// for the VLMAX instead. This reduces register pressure slightly.
const unsigned VLMAX = computeVLMAX(ST.getRealMaxVLen(), SEW, VLMul);
if (ST.getRealMinVLen() == ST.getRealMaxVLen() && VLMAX <= 31)
InstrInfo.setAVLImm(VLMAX);
else
Expand All @@ -873,7 +874,18 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
else
InstrInfo.setAVLImm(Imm);
} else {
InstrInfo.setAVLReg(VLOp.getReg());
Register Reg = VLOp.getReg();
// If VL is a register, it may be a materialized constant that didn't fit
// into an uimm5. If we also know the exact VLEN, and the VL is equal to
// the exact VLEN, use the X0 encoding so we don't need the ADDI.
// doLocalPostpass will remove the ADDI if it's dead.
if (ST.getRealMinVLen() == ST.getRealMaxVLen() &&
VLOp.getReg().isVirtual())
if (auto *VLDef = MRI->getVRegDef(VLOp.getReg());
VLDef && isNonZeroLoadImmediate(*VLDef) &&
VLDef->getOperand(2).getImm() == VLMAX)
Reg = RISCV::X0;
InstrInfo.setAVLReg(Reg);
}
} else {
assert(isScalarExtractInstr(MI));
Expand Down