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[NVPTX] Add 'activemask' builtin and intrinsic support #79768

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Jan 29, 2024
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[NVPTX] Add 'activemask' builtin and intrinsic support #79768

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2c7049d
[NVPTX] Add 'activemask' builtin and intrinsic support
jhuber6 Jan 28, 2024
04a1b84
AddHasSideEffects
jhuber6 Jan 29, 2024
b5f36a7
Update PTX version according to Artems instruction
jhuber6 Jan 29, 2024
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8 changes: 7 additions & 1 deletion clang/include/clang/Basic/BuiltinsNVPTX.def
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Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,7 @@
#pragma push_macro("PTX42")
#pragma push_macro("PTX60")
#pragma push_macro("PTX61")
#pragma push_macro("PTX62")
#pragma push_macro("PTX63")
#pragma push_macro("PTX64")
#pragma push_macro("PTX65")
Expand Down Expand Up @@ -76,7 +77,8 @@
#define PTX65 "ptx65|" PTX70
#define PTX64 "ptx64|" PTX65
#define PTX63 "ptx63|" PTX64
#define PTX61 "ptx61|" PTX63
#define PTX62 "ptx62|" PTX63
#define PTX61 "ptx61|" PTX62
#define PTX60 "ptx60|" PTX61
#define PTX42 "ptx42|" PTX60

Expand Down Expand Up @@ -632,6 +634,9 @@ TARGET_BUILTIN(__nvvm_vote_any_sync, "bUib", "", PTX60)
TARGET_BUILTIN(__nvvm_vote_uni_sync, "bUib", "", PTX60)
TARGET_BUILTIN(__nvvm_vote_ballot_sync, "UiUib", "", PTX60)

// Mask
TARGET_BUILTIN(__nvvm_activemask, "i", "n", PTX62)

// Match
TARGET_BUILTIN(__nvvm_match_any_sync_i32, "UiUiUi", "", AND(SM_70,PTX60))
TARGET_BUILTIN(__nvvm_match_any_sync_i64, "UiUiWi", "", AND(SM_70,PTX60))
Expand Down Expand Up @@ -1065,6 +1070,7 @@ TARGET_BUILTIN(__nvvm_getctarank_shared_cluster, "iv*3", "", AND(SM_90,PTX78))
#pragma pop_macro("PTX42")
#pragma pop_macro("PTX60")
#pragma pop_macro("PTX61")
#pragma pop_macro("PTX62")
#pragma pop_macro("PTX63")
#pragma pop_macro("PTX64")
#pragma pop_macro("PTX65")
Expand Down
16 changes: 12 additions & 4 deletions clang/test/CodeGen/builtins-nvptx.c
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Expand Up @@ -5,16 +5,16 @@
// RUN: %clang_cc1 -ffp-contract=off -triple nvptx64-unknown-unknown -target-cpu sm_80 -target-feature +ptx70 \
// RUN: -fcuda-is-device -S -emit-llvm -o - -x cuda %s \
// RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK_PTX70_SM80 -check-prefix=LP64 %s
// RUN: %clang_cc1 -ffp-contract=off -triple nvptx-unknown-unknown -target-cpu sm_60 \
// RUN: %clang_cc1 -ffp-contract=off -triple nvptx-unknown-unknown -target-cpu sm_60 -target-feature +ptx62 \
// RUN: -fcuda-is-device -S -emit-llvm -o - -x cuda %s \
// RUN: | FileCheck -check-prefix=CHECK -check-prefix=LP32 %s
// RUN: %clang_cc1 -ffp-contract=off -triple nvptx64-unknown-unknown -target-cpu sm_60 \
// RUN: %clang_cc1 -ffp-contract=off -triple nvptx64-unknown-unknown -target-cpu sm_60 -target-feature +ptx62 \
// RUN: -fcuda-is-device -S -emit-llvm -o - -x cuda %s \
// RUN: | FileCheck -check-prefix=CHECK -check-prefix=LP64 %s
// RUN: %clang_cc1 -ffp-contract=off -triple nvptx64-unknown-unknown -target-cpu sm_61 \
// RUN: %clang_cc1 -ffp-contract=off -triple nvptx64-unknown-unknown -target-cpu sm_61 -target-feature +ptx62 \
// RUN: -fcuda-is-device -S -emit-llvm -o - -x cuda %s \
// RUN: | FileCheck -check-prefix=CHECK -check-prefix=LP64 %s
// RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_53 \
// RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_53 -target-feature +ptx62 \
// RUN: -DERROR_CHECK -fcuda-is-device -S -o /dev/null -x cuda -verify %s
// RUN: %clang_cc1 -ffp-contract=off -triple nvptx-unknown-unknown -target-cpu sm_86 -target-feature +ptx72 \
// RUN: -fcuda-is-device -S -emit-llvm -o - -x cuda %s \
Expand Down Expand Up @@ -165,6 +165,14 @@ __device__ void sync() {

}

__device__ void activemask() {

// CHECK: call i32 @llvm.nvvm.activemask()

__nvvm_activemask();

}


// NVVM intrinsics

Expand Down
8 changes: 8 additions & 0 deletions llvm/include/llvm/IR/IntrinsicsNVVM.td
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Original file line number Diff line number Diff line change
Expand Up @@ -4599,6 +4599,14 @@ def int_nvvm_vote_ballot_sync :
[IntrInaccessibleMemOnly, IntrConvergent, IntrNoCallback], "llvm.nvvm.vote.ballot.sync">,
ClangBuiltin<"__nvvm_vote_ballot_sync">;

//
// ACTIVEMASK
//
def int_nvvm_activemask :
Intrinsic<[llvm_i32_ty], [],
[IntrInaccessibleMemOnly, IntrConvergent, IntrNoCallback], "llvm.nvvm.activemask">,
ClangBuiltin<"__nvvm_activemask">;

//
// MATCH.SYNC
//
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/NVPTX/NVPTX.td
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Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ foreach sm = [20, 21, 30, 32, 35, 37, 50, 52, 53,

def SM90a: FeatureSM<"90a", 901>;

foreach version = [32, 40, 41, 42, 43, 50, 60, 61, 63, 64, 65,
foreach version = [32, 40, 41, 42, 43, 50, 60, 61, 62, 63, 64, 65,
70, 71, 72, 73, 74, 75, 76, 77, 78, 80, 81, 82, 83] in
def PTX#version: FeaturePTX<version>;

Expand All @@ -65,7 +65,7 @@ def : Proc<"sm_61", [SM61, PTX50]>;
def : Proc<"sm_62", [SM62, PTX50]>;
def : Proc<"sm_70", [SM70, PTX60]>;
def : Proc<"sm_72", [SM72, PTX61]>;
def : Proc<"sm_75", [SM75, PTX63]>;
def : Proc<"sm_75", [SM75, PTX62, PTX63]>;
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Why are we adding PTX62 here?

According to PTX docs sm_75 has been introduced in PTX ISA 6.3 in CUDA-10.0.

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Yeah I wasn't sure where it should go. The docs specify it's PTX62, but I couldn't find which one that came from, so I just put it before 63. Maybe on 72?

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What are you trying to do with PTX62 feature to start with? Why do you need to add it here to start with?

In general, the features will be supplied externally. This particular place just sets the minimum required to support this particular GPU variant.

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Okay, so I can just get rid of it for this definition and it will still work? I could've just said it came with 63 and been lazy I suppose.

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I'm confused a bit here. Constraints on PTX version for GPU and for instrunctions are independent. You need both satisfied in order to use a given instruction on a given GPU.

So, to use activemask on sm_75, you do need PTX63.
To use it on sm_52, you only need PTX62.

You do not need to change anything here. You already have correct predicates applied to the instruction itself and to the target builtin.

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Okay, so I'll remove it from the definition here and just add the PTX62. I don't have the fullest understanding of how this pTX stuff works.

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Should be fixed now, also I added the one for nanosleep in #79888.

def : Proc<"sm_80", [SM80, PTX70]>;
def : Proc<"sm_86", [SM86, PTX71]>;
def : Proc<"sm_87", [SM87, PTX74]>;
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
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Expand Up @@ -263,6 +263,12 @@ multiclass MATCH_ANY_SYNC<NVPTXRegClass regclass, string ptxtype, Intrinsic IntO
Requires<[hasPTX<60>, hasSM<70>]>;
}

// activemask.b32
def ACTIVEMASK : NVPTXInst<(outs Int32Regs:$dest), (ins),
"activemask.b32 \t$dest;",
[(set Int32Regs:$dest, (int_nvvm_activemask))]>,
Requires<[hasPTX<62>, hasSM<30>]>;

defm MATCH_ANY_SYNC_32 : MATCH_ANY_SYNC<Int32Regs, "b32", int_nvvm_match_any_sync_i32,
i32imm>;
defm MATCH_ANY_SYNC_64 : MATCH_ANY_SYNC<Int64Regs, "b64", int_nvvm_match_any_sync_i64,
Expand Down
38 changes: 38 additions & 0 deletions llvm/test/CodeGen/NVPTX/activemask.ll
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@@ -0,0 +1,38 @@
; RUN: llc < %s -march=nvptx64 -O2 -mcpu=sm_52 -mattr=+ptx62 | FileCheck %s
; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_52 -mattr=+ptx62 | %ptxas-verify %}

declare i32 @llvm.nvvm.activemask()

; CHECK-LABEL: activemask(
;
; CHECK: activemask.b32 %[[REG:.+]];
; CHECK-NEXT: st.param.b32 [func_retval0+0], %[[REG]];
; CHECK-NEXT: ret;
define dso_local i32 @activemask() {
entry:
%mask = call i32 @llvm.nvvm.activemask()
ret i32 %mask
}

; CHECK-LABEL: convergent(
;
; CHECK: activemask.b32 %[[REG:.+]];
; CHECK: activemask.b32 %[[REG]];
; CHECK: .param.b32 [func_retval0+0], %[[REG]];
; CHECK-NEXT: ret;
define dso_local i32 @convergent(i1 %cond) {
entry:
br i1 %cond, label %if.else, label %if.then

if.then:
%0 = call i32 @llvm.nvvm.activemask()
br label %if.end

if.else:
%1 = call i32 @llvm.nvvm.activemask()
br label %if.end

if.end:
%mask = phi i32 [ %0, %if.then ], [ %1, %if.else ]
ret i32 %mask
}