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Fix Passing TargetOptions by Value in TargetMachines for AMDGPU #79866

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Merged
merged 3 commits into from
Feb 1, 2024
Merged

Fix Passing TargetOptions by Value in TargetMachines for AMDGPU #79866

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b94283d
Fixed passing TargetOptions by value in TargetMachines for AMDGPU.
matinraayai Jan 29, 2024
097de69
Fixed clang formatting issue.
matinraayai Jan 29, 2024
28b0585
Empty commit to re-trigger the CI
matinraayai Jan 30, 2024
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -571,7 +571,7 @@ static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {

AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
TargetOptions Options,
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OptLevel)
Expand Down Expand Up @@ -863,7 +863,7 @@ AMDGPUTargetMachine::getAddressSpaceForPseudoSourceKind(unsigned Kind) const {

GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
TargetOptions Options,
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
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Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ class AMDGPUTargetMachine : public LLVMTargetMachine {
static bool EnableLowerModuleLDS;

AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, TargetOptions Options,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOptLevel OL);
~AMDGPUTargetMachine() override;
Expand Down Expand Up @@ -78,7 +78,7 @@ class GCNTargetMachine final : public AMDGPUTargetMachine {

public:
GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, TargetOptions Options,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@ static MachineSchedRegistry R600SchedRegistry("r600",

R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
TargetOptions Options,
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
CodeGenOptLevel OL, bool JIT)
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/R600TargetMachine.h
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ class R600TargetMachine final : public AMDGPUTargetMachine {

public:
R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, TargetOptions Options,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
Expand Down