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[X86][MC] Support encoding/decoding for APX variant LZCNT/TZCNT/POPCNT instructions #79954

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Merged
merged 1 commit into from
Jan 31, 2024
Merged

[X86][MC] Support encoding/decoding for APX variant LZCNT/TZCNT/POPCNT instructions #79954

merged 1 commit into from
Jan 31, 2024

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XinWang10
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Two variants: promoted legacy, NF (no flags update).

The syntax of NF instructions is aligned with GNU binutils.
https://sourceware.org/pipermail/binutils/2023-September/129545.html

@llvmbot llvmbot added backend:X86 mc Machine (object) code labels Jan 30, 2024
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llvmbot commented Jan 30, 2024 •
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Author: None (XinWang10)

Changes

Two variants: promoted legacy, NF (no flags update).

The syntax of NF instructions is aligned with GNU binutils.
https://sourceware.org/pipermail/binutils/2023-September/129545.html

Patch is 28.60 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/79954.diff

12 Files Affected:

  • (modified) llvm/lib/Target/X86/X86InstrMisc.td (+36-52)
  • (modified) llvm/lib/Target/X86/X86InstrSSE.td (+11-30)
  • (added) llvm/test/MC/Disassembler/X86/apx/lzcnt.txt (+50)
  • (added) llvm/test/MC/Disassembler/X86/apx/popcnt.txt (+50)
  • (added) llvm/test/MC/Disassembler/X86/apx/tzcnt.txt (+50)
  • (added) llvm/test/MC/X86/apx/lzcnt-att.s (+38)
  • (added) llvm/test/MC/X86/apx/lzcnt-intel.s (+38)
  • (added) llvm/test/MC/X86/apx/popcnt-att.s (+38)
  • (added) llvm/test/MC/X86/apx/popcnt-intel.s (+38)
  • (added) llvm/test/MC/X86/apx/tzcnt-att.s (+38)
  • (added) llvm/test/MC/X86/apx/tzcnt-intel.s (+38)
  • (modified) llvm/test/TableGen/x86-fold-tables.inc (+9)
diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td
index bd178f3a27fe7..a39b805927137 100644
--- a/llvm/lib/Target/X86/X86InstrMisc.td
+++ b/llvm/lib/Target/X86/X86InstrMisc.td
@@ -1159,67 +1159,51 @@ let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in {
 //===----------------------------------------------------------------------===//
 // LZCNT Instruction
 //
+multiclass Lzcnt<bits<8> o, string m, SDPatternOperator node, X86TypeInfo t,
+                 SchedWrite schedrr, SchedWrite schedrm, string suffix = ""> {
+  def rr#suffix : ITy<o, MRMSrcReg, t, (outs t.RegClass:$dst),
+                      (ins t.RegClass:$src1), m, unaryop_ndd_args,
+                      [(set t.RegClass:$dst, (node t.RegClass:$src1)),
+                                              (implicit EFLAGS)]>,
+                  TB, Sched<[schedrr]>;
+  def rm#suffix : ITy<o, MRMSrcMem, t, (outs t.RegClass:$dst),
+                      (ins t.MemOperand:$src1), m, unaryop_ndd_args,
+                      [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1))),
+                                              (implicit EFLAGS)]>,
+                  TB, Sched<[schedrm]>;
+}
+
 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
-  def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
-                    "lzcnt{w}\t{$src, $dst|$dst, $src}",
-                    [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>,
-                    TB, XS, OpSize16, Sched<[WriteLZCNT]>;
-  def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
-                    "lzcnt{w}\t{$src, $dst|$dst, $src}",
-                    [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
-                     (implicit EFLAGS)]>, TB, XS, OpSize16, Sched<[WriteLZCNTLd]>;
-
-  def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
-                    "lzcnt{l}\t{$src, $dst|$dst, $src}",
-                    [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>,
-                    TB, XS, OpSize32, Sched<[WriteLZCNT]>;
-  def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
-                    "lzcnt{l}\t{$src, $dst|$dst, $src}",
-                    [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
-                     (implicit EFLAGS)]>, TB, XS, OpSize32, Sched<[WriteLZCNTLd]>;
-
-  def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
-                     "lzcnt{q}\t{$src, $dst|$dst, $src}",
-                     [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
-                     TB, XS, Sched<[WriteLZCNT]>;
-  def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
-                     "lzcnt{q}\t{$src, $dst|$dst, $src}",
-                     [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
-                      (implicit EFLAGS)]>, TB, XS, Sched<[WriteLZCNTLd]>;
+  defm LZCNT16 : Lzcnt<0xBD, "lzcnt", ctlz, Xi16, WriteLZCNT, WriteLZCNTLd>, OpSize16, XS;
+  defm LZCNT32 : Lzcnt<0xBD, "lzcnt", ctlz, Xi32, WriteLZCNT, WriteLZCNTLd>, OpSize32, XS;
+  defm LZCNT64 : Lzcnt<0xBD, "lzcnt", ctlz, Xi64, WriteLZCNT, WriteLZCNTLd>, XS;
+
+  defm LZCNT16 : Lzcnt<0xF5, "lzcnt", null_frag, Xi16, WriteLZCNT, WriteLZCNTLd, "_EVEX">, PL, PD;
+  defm LZCNT32 : Lzcnt<0xF5, "lzcnt", null_frag, Xi32, WriteLZCNT, WriteLZCNTLd, "_EVEX">, PL;
+  defm LZCNT64 : Lzcnt<0xF5, "lzcnt", null_frag, Xi64, WriteLZCNT, WriteLZCNTLd, "_EVEX">, PL;
 }
 
+defm LZCNT16 : Lzcnt<0xF5, "lzcnt", null_frag, Xi16, WriteLZCNT, WriteLZCNTLd, "_NF">, NF, PD;
+defm LZCNT32 : Lzcnt<0xF5, "lzcnt", null_frag, Xi32, WriteLZCNT, WriteLZCNTLd, "_NF">, NF;
+defm LZCNT64 : Lzcnt<0xF5, "lzcnt", null_frag, Xi64, WriteLZCNT, WriteLZCNTLd, "_NF">, NF;
+
 //===----------------------------------------------------------------------===//
 // BMI Instructions
 //
 let Predicates = [HasBMI], Defs = [EFLAGS] in {
-  def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
-                    "tzcnt{w}\t{$src, $dst|$dst, $src}",
-                    [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>,
-                    TB, XS, OpSize16, Sched<[WriteTZCNT]>;
-  def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
-                    "tzcnt{w}\t{$src, $dst|$dst, $src}",
-                    [(set GR16:$dst, (cttz (loadi16 addr:$src))),
-                     (implicit EFLAGS)]>, TB, XS, OpSize16, Sched<[WriteTZCNTLd]>;
-
-  def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
-                    "tzcnt{l}\t{$src, $dst|$dst, $src}",
-                    [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>,
-                    TB, XS, OpSize32, Sched<[WriteTZCNT]>;
-  def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
-                    "tzcnt{l}\t{$src, $dst|$dst, $src}",
-                    [(set GR32:$dst, (cttz (loadi32 addr:$src))),
-                     (implicit EFLAGS)]>, TB, XS, OpSize32, Sched<[WriteTZCNTLd]>;
-
-  def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
-                     "tzcnt{q}\t{$src, $dst|$dst, $src}",
-                     [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
-                     TB, XS, Sched<[WriteTZCNT]>;
-  def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
-                     "tzcnt{q}\t{$src, $dst|$dst, $src}",
-                     [(set GR64:$dst, (cttz (loadi64 addr:$src))),
-                      (implicit EFLAGS)]>, TB, XS, Sched<[WriteTZCNTLd]>;
+  defm TZCNT16 : Lzcnt<0xBC, "tzcnt", cttz, Xi16, WriteTZCNT, WriteTZCNTLd>, OpSize16, XS;
+  defm TZCNT32 : Lzcnt<0xBC, "tzcnt", cttz, Xi32, WriteTZCNT, WriteTZCNTLd>, OpSize32, XS;
+  defm TZCNT64 : Lzcnt<0xBC, "tzcnt", cttz, Xi64, WriteTZCNT, WriteTZCNTLd>, XS;
+
+  defm TZCNT16 : Lzcnt<0xF4, "tzcnt", null_frag, Xi16, WriteTZCNT, WriteTZCNTLd, "_EVEX">, PL, PD;
+  defm TZCNT32 : Lzcnt<0xF4, "tzcnt", null_frag, Xi32, WriteTZCNT, WriteTZCNTLd, "_EVEX">, PL;
+  defm TZCNT64 : Lzcnt<0xF4, "tzcnt", null_frag, Xi64, WriteTZCNT, WriteTZCNTLd, "_EVEX">, PL;
 }
 
+defm TZCNT16 : Lzcnt<0xF4, "tzcnt", null_frag, Xi16, WriteTZCNT, WriteTZCNTLd, "_NF">, NF, PD;
+defm TZCNT32 : Lzcnt<0xF4, "tzcnt", null_frag, Xi32, WriteTZCNT, WriteTZCNTLd, "_NF">, NF;
+defm TZCNT64 : Lzcnt<0xF4, "tzcnt", null_frag, Xi64, WriteTZCNT, WriteTZCNTLd, "_NF">, NF;
+
 multiclass Bls<string m, Format RegMRM, Format MemMRM, X86TypeInfo t, string Suffix = ""> {
   let SchedRW = [WriteBLS] in {
     def rr#Suffix : UnaryOpR<0xF3, RegMRM, m, unaryop_ndd_args, t,
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 7d94fec9a354d..8c7183bf80602 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -5757,38 +5757,19 @@ defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64,
 //===----------------------------------------------------------------------===//
 
 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
-  def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
-                     "popcnt{w}\t{$src, $dst|$dst, $src}",
-                     [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
-                     Sched<[WritePOPCNT]>, OpSize16, TB, XS;
-  def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
-                     "popcnt{w}\t{$src, $dst|$dst, $src}",
-                     [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
-                      (implicit EFLAGS)]>,
-                      Sched<[WritePOPCNT.Folded]>, OpSize16, TB, XS;
-
-  def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
-                     "popcnt{l}\t{$src, $dst|$dst, $src}",
-                     [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
-                     Sched<[WritePOPCNT]>, OpSize32, TB, XS;
-
-  def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
-                     "popcnt{l}\t{$src, $dst|$dst, $src}",
-                     [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
-                      (implicit EFLAGS)]>,
-                      Sched<[WritePOPCNT.Folded]>, OpSize32, TB, XS;
-
-  def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
-                      "popcnt{q}\t{$src, $dst|$dst, $src}",
-                      [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
-                      Sched<[WritePOPCNT]>, TB, XS;
-  def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
-                      "popcnt{q}\t{$src, $dst|$dst, $src}",
-                      [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
-                       (implicit EFLAGS)]>,
-                       Sched<[WritePOPCNT.Folded]>, TB, XS;
+  defm POPCNT16 : Lzcnt<0xB8, "popcnt", ctpop, Xi16, WritePOPCNT, WritePOPCNT.Folded>, OpSize16, XS;
+  defm POPCNT32 : Lzcnt<0xB8, "popcnt", ctpop, Xi32, WritePOPCNT, WritePOPCNT.Folded>, OpSize32, XS;
+  defm POPCNT64 : Lzcnt<0xB8, "popcnt", ctpop, Xi64, WritePOPCNT, WritePOPCNT.Folded>, XS;
+
+  defm POPCNT16 : Lzcnt<0x88, "popcnt", null_frag, Xi16, WritePOPCNT, WritePOPCNT.Folded, "_EVEX">, PL, PD;
+  defm POPCNT32 : Lzcnt<0x88, "popcnt", null_frag, Xi32, WritePOPCNT, WritePOPCNT.Folded, "_EVEX">, PL;
+  defm POPCNT64 : Lzcnt<0x88, "popcnt", null_frag, Xi64, WritePOPCNT, WritePOPCNT.Folded, "_EVEX">, PL;
 }
 
+defm POPCNT16 : Lzcnt<0x88, "popcnt", null_frag, Xi16, WritePOPCNT, WritePOPCNT.Folded, "_NF">, NF, PD;
+defm POPCNT32 : Lzcnt<0x88, "popcnt", null_frag, Xi32, WritePOPCNT, WritePOPCNT.Folded, "_NF">, NF;
+defm POPCNT64 : Lzcnt<0x88, "popcnt", null_frag, Xi64, WritePOPCNT, WritePOPCNT.Folded, "_NF">, NF;
+
 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
                                  SDNode OpNode, PatFrag ld_frag,
diff --git a/llvm/test/MC/Disassembler/X86/apx/lzcnt.txt b/llvm/test/MC/Disassembler/X86/apx/lzcnt.txt
new file mode 100644
index 0000000000000..6e41cf4c2b04f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/lzcnt.txt
@@ -0,0 +1,50 @@
+# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
+# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
+
+# ATT:   {evex}	lzcntw	%dx, %ax
+# INTEL: {evex}	lzcnt	ax, dx
+0x62,0xf4,0x7d,0x08,0xf5,0xc2
+
+# ATT:   {nf}	lzcntw	%dx, %ax
+# INTEL: {nf}	lzcnt	ax, dx
+0x62,0xf4,0x7d,0x0c,0xf5,0xc2
+
+# ATT:   {evex}	lzcntl	%ecx, %edx
+# INTEL: {evex}	lzcnt	edx, ecx
+0x62,0xf4,0x7c,0x08,0xf5,0xd1
+
+# ATT:   {nf}	lzcntl	%ecx, %edx
+# INTEL: {nf}	lzcnt	edx, ecx
+0x62,0xf4,0x7c,0x0c,0xf5,0xd1
+
+# ATT:   {evex}	lzcntq	%r9, %r15
+# INTEL: {evex}	lzcnt	r15, r9
+0x62,0x54,0xfc,0x08,0xf5,0xf9
+
+# ATT:   {nf}	lzcntq	%r9, %r15
+# INTEL: {nf}	lzcnt	r15, r9
+0x62,0x54,0xfc,0x0c,0xf5,0xf9
+
+# ATT:   {evex}	lzcntw	123(%r8,%rax,4), %dx
+# INTEL: {evex}	lzcnt	dx, word ptr [r8 + 4*rax + 123]
+0x62,0xd4,0x7d,0x08,0xf5,0x54,0x80,0x7b
+
+# ATT:   {nf}	lzcntw	123(%r8,%rax,4), %dx
+# INTEL: {nf}	lzcnt	dx, word ptr [r8 + 4*rax + 123]
+0x62,0xd4,0x7d,0x0c,0xf5,0x54,0x80,0x7b
+
+# ATT:   {evex}	lzcntl	123(%r8,%rax,4), %ecx
+# INTEL: {evex}	lzcnt	ecx, dword ptr [r8 + 4*rax + 123]
+0x62,0xd4,0x7c,0x08,0xf5,0x4c,0x80,0x7b
+
+# ATT:   {nf}	lzcntl	123(%r8,%rax,4), %ecx
+# INTEL: {nf}	lzcnt	ecx, dword ptr [r8 + 4*rax + 123]
+0x62,0xd4,0x7c,0x0c,0xf5,0x4c,0x80,0x7b
+
+# ATT:   {evex}	lzcntq	123(%r8,%rax,4), %r9
+# INTEL: {evex}	lzcnt	r9, qword ptr [r8 + 4*rax + 123]
+0x62,0x54,0xfc,0x08,0xf5,0x4c,0x80,0x7b
+
+# ATT:   {nf}	lzcntq	123(%r8,%rax,4), %r9
+# INTEL: {nf}	lzcnt	r9, qword ptr [r8 + 4*rax + 123]
+0x62,0x54,0xfc,0x0c,0xf5,0x4c,0x80,0x7b
diff --git a/llvm/test/MC/Disassembler/X86/apx/popcnt.txt b/llvm/test/MC/Disassembler/X86/apx/popcnt.txt
new file mode 100644
index 0000000000000..d6ceef62f286f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/popcnt.txt
@@ -0,0 +1,50 @@
+# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
+# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
+
+# ATT:   {evex}	popcntw	%dx, %ax
+# INTEL: {evex}	popcnt	ax, dx
+0x62,0xf4,0x7d,0x08,0x88,0xc2
+
+# ATT:   {nf}	popcntw	%dx, %ax
+# INTEL: {nf}	popcnt	ax, dx
+0x62,0xf4,0x7d,0x0c,0x88,0xc2
+
+# ATT:   {evex}	popcntl	%ecx, %edx
+# INTEL: {evex}	popcnt	edx, ecx
+0x62,0xf4,0x7c,0x08,0x88,0xd1
+
+# ATT:   {nf}	popcntl	%ecx, %edx
+# INTEL: {nf}	popcnt	edx, ecx
+0x62,0xf4,0x7c,0x0c,0x88,0xd1
+
+# ATT:   {evex}	popcntq	%r9, %r15
+# INTEL: {evex}	popcnt	r15, r9
+0x62,0x54,0xfc,0x08,0x88,0xf9
+
+# ATT:   {nf}	popcntq	%r9, %r15
+# INTEL: {nf}	popcnt	r15, r9
+0x62,0x54,0xfc,0x0c,0x88,0xf9
+
+# ATT:   {evex}	popcntw	123(%r8,%rax,4), %dx
+# INTEL: {evex}	popcnt	dx, word ptr [r8 + 4*rax + 123]
+0x62,0xd4,0x7d,0x08,0x88,0x54,0x80,0x7b
+
+# ATT:   {nf}	popcntw	123(%r8,%rax,4), %dx
+# INTEL: {nf}	popcnt	dx, word ptr [r8 + 4*rax + 123]
+0x62,0xd4,0x7d,0x0c,0x88,0x54,0x80,0x7b
+
+# ATT:   {evex}	popcntl	123(%r8,%rax,4), %ecx
+# INTEL: {evex}	popcnt	ecx, dword ptr [r8 + 4*rax + 123]
+0x62,0xd4,0x7c,0x08,0x88,0x4c,0x80,0x7b
+
+# ATT:   {nf}	popcntl	123(%r8,%rax,4), %ecx
+# INTEL: {nf}	popcnt	ecx, dword ptr [r8 + 4*rax + 123]
+0x62,0xd4,0x7c,0x0c,0x88,0x4c,0x80,0x7b
+
+# ATT:   {evex}	popcntq	123(%r8,%rax,4), %r9
+# INTEL: {evex}	popcnt	r9, qword ptr [r8 + 4*rax + 123]
+0x62,0x54,0xfc,0x08,0x88,0x4c,0x80,0x7b
+
+# ATT:   {nf}	popcntq	123(%r8,%rax,4), %r9
+# INTEL: {nf}	popcnt	r9, qword ptr [r8 + 4*rax + 123]
+0x62,0x54,0xfc,0x0c,0x88,0x4c,0x80,0x7b
diff --git a/llvm/test/MC/Disassembler/X86/apx/tzcnt.txt b/llvm/test/MC/Disassembler/X86/apx/tzcnt.txt
new file mode 100644
index 0000000000000..8c404f2e176fd
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/tzcnt.txt
@@ -0,0 +1,50 @@
+# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
+# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
+
+# ATT:   {evex}	tzcntw	%dx, %ax
+# INTEL: {evex}	tzcnt	ax, dx
+0x62,0xf4,0x7d,0x08,0xf4,0xc2
+
+# ATT:   {nf}	tzcntw	%dx, %ax
+# INTEL: {nf}	tzcnt	ax, dx
+0x62,0xf4,0x7d,0x0c,0xf4,0xc2
+
+# ATT:   {evex}	tzcntl	%ecx, %edx
+# INTEL: {evex}	tzcnt	edx, ecx
+0x62,0xf4,0x7c,0x08,0xf4,0xd1
+
+# ATT:   {nf}	tzcntl	%ecx, %edx
+# INTEL: {nf}	tzcnt	edx, ecx
+0x62,0xf4,0x7c,0x0c,0xf4,0xd1
+
+# ATT:   {evex}	tzcntq	%r9, %r15
+# INTEL: {evex}	tzcnt	r15, r9
+0x62,0x54,0xfc,0x08,0xf4,0xf9
+
+# ATT:   {nf}	tzcntq	%r9, %r15
+# INTEL: {nf}	tzcnt	r15, r9
+0x62,0x54,0xfc,0x0c,0xf4,0xf9
+
+# ATT:   {evex}	tzcntw	123(%r8,%rax,4), %dx
+# INTEL: {evex}	tzcnt	dx, word ptr [r8 + 4*rax + 123]
+0x62,0xd4,0x7d,0x08,0xf4,0x54,0x80,0x7b
+
+# ATT:   {nf}	tzcntw	123(%r8,%rax,4), %dx
+# INTEL: {nf}	tzcnt	dx, word ptr [r8 + 4*rax + 123]
+0x62,0xd4,0x7d,0x0c,0xf4,0x54,0x80,0x7b
+
+# ATT:   {evex}	tzcntl	123(%r8,%rax,4), %ecx
+# INTEL: {evex}	tzcnt	ecx, dword ptr [r8 + 4*rax + 123]
+0x62,0xd4,0x7c,0x08,0xf4,0x4c,0x80,0x7b
+
+# ATT:   {nf}	tzcntl	123(%r8,%rax,4), %ecx
+# INTEL: {nf}	tzcnt	ecx, dword ptr [r8 + 4*rax + 123]
+0x62,0xd4,0x7c,0x0c,0xf4,0x4c,0x80,0x7b
+
+# ATT:   {evex}	tzcntq	123(%r8,%rax,4), %r9
+# INTEL: {evex}	tzcnt	r9, qword ptr [r8 + 4*rax + 123]
+0x62,0x54,0xfc,0x08,0xf4,0x4c,0x80,0x7b
+
+# ATT:   {nf}	tzcntq	123(%r8,%rax,4), %r9
+# INTEL: {nf}	tzcnt	r9, qword ptr [r8 + 4*rax + 123]
+0x62,0x54,0xfc,0x0c,0xf4,0x4c,0x80,0x7b
diff --git a/llvm/test/MC/X86/apx/lzcnt-att.s b/llvm/test/MC/X86/apx/lzcnt-att.s
new file mode 100644
index 0000000000000..ba5c4b56cd031
--- /dev/null
+++ b/llvm/test/MC/X86/apx/lzcnt-att.s
@@ -0,0 +1,38 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+# CHECK: {evex}	lzcntw	%dx, %ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf5,0xc2]
+         {evex}	lzcntw	%dx, %ax
+# CHECK: {nf}	lzcntw	%dx, %ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xf5,0xc2]
+         {nf}	lzcntw	%dx, %ax
+# CHECK: {evex}	lzcntl	%ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf5,0xd1]
+         {evex}	lzcntl	%ecx, %edx
+# CHECK: {nf}	lzcntl	%ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xf5,0xd1]
+         {nf}	lzcntl	%ecx, %edx
+# CHECK: {evex}	lzcntq	%r9, %r15
+# CHECK: encoding: [0x62,0x54,0xfc,0x08,0xf5,0xf9]
+         {evex}	lzcntq	%r9, %r15
+# CHECK: {nf}	lzcntq	%r9, %r15
+# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0xf5,0xf9]
+         {nf}	lzcntq	%r9, %r15
+# CHECK: {evex}	lzcntw	123(%r8,%rax,4), %dx
+# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xf5,0x54,0x80,0x7b]
+         {evex}	lzcntw	123(%r8,%rax,4), %dx
+# CHECK: {nf}	lzcntw	123(%r8,%rax,4), %dx
+# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xf5,0x54,0x80,0x7b]
+         {nf}	lzcntw	123(%r8,%rax,4), %dx
+# CHECK: {evex}	lzcntl	123(%r8,%rax,4), %ecx
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xf5,0x4c,0x80,0x7b]
+         {evex}	lzcntl	123(%r8,%rax,4), %ecx
+# CHECK: {nf}	lzcntl	123(%r8,%rax,4), %ecx
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xf5,0x4c,0x80,0x7b]
+         {nf}	lzcntl	123(%r8,%rax,4), %ecx
+# CHECK: {evex}	lzcntq	123(%r8,%rax,4), %r9
+# CHECK: encoding: [0x62,0x54,0xfc,0x08,0xf5,0x4c,0x80,0x7b]
+         {evex}	lzcntq	123(%r8,%rax,4), %r9
+# CHECK: {nf}	lzcntq	123(%r8,%rax,4), %r9
+# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0xf5,0x4c,0x80,0x7b]
+         {nf}	lzcntq	123(%r8,%rax,4), %r9
diff --git a/llvm/test/MC/X86/apx/lzcnt-intel.s b/llvm/test/MC/X86/apx/lzcnt-intel.s
new file mode 100644
index 0000000000000..c3301be6bc275
--- /dev/null
+++ b/llvm/test/MC/X86/apx/lzcnt-intel.s
@@ -0,0 +1,38 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s
+
+# CHECK: {evex}	lzcnt	ax, dx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf5,0xc2]
+         {evex}	lzcnt	ax, dx
+# CHECK: {nf}	lzcnt	ax, dx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xf5,0xc2]
+         {nf}	lzcnt	ax, dx
+# CHECK: {evex}	lzcnt	edx, ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf5,0xd1]
+         {evex}	lzcnt	edx, ecx
+# CHECK: {nf}	lzcnt	edx, ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xf5,0xd1]
+         {nf}	lzcnt	edx, ecx
+# CHECK: {evex}	lzcnt	r15, r9
+# CHECK: encoding: [0x62,0x54,0xfc,0x08,0xf5,0xf9]
+         {evex}	lzcnt	r15, r9
+# CHECK: {nf}	lzcnt	r15, r9
+# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0xf5,0xf9]
+         {nf}	lzcnt	r15, r9
+# CHECK: {evex}	lzcnt	dx, word ptr [r8 + 4*rax + 123]
+# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xf5,0x54,0x80,0x7b]
+         {evex}	lzcnt	dx, word ptr [r8 + 4*rax + 123]
+# CHECK: {nf}	lzcnt	dx, word ptr [r8 + 4*rax + 123]
+# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xf5,0x54,0x80,0x7b]
+         {nf}	lzcnt	dx, word ptr [r8 + 4*rax + 123]
+# CHECK: {evex}	lzcnt	ecx, dword ptr [r8 + 4*rax + 123]
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xf5,0x4c,0x80,0x7b]
+         {evex}	lzcnt	ecx, dword ptr [r8 + 4*rax + 123]
+# CHECK: {nf}	lzcnt	ecx, dword ptr [r8 + 4*rax + 123]
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xf5,0x4c,0x80,0x7b]
+         {nf}	lzcnt	ecx, dword ptr [r8 + 4*rax + 123]
+# CHECK: {evex}	lzcnt	r9, qword ptr [r8 + 4*rax + 123]
+# CHECK: encoding: [0x62,0x54,0xfc,0x08,0xf5,0x4c,0x80,0x7b]
+         {evex}	lzcnt	r9, qword ptr [r8 + 4*rax + 123]
+# CHECK: {nf}	lzcnt	r9, qword ptr [r8 + 4*rax + 123]
+# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0xf5,0x4c,0x80,0x7b]
+         {nf}	lzcnt	r9, qword ptr [r8 + 4*rax + 123]
diff --git a/llvm/test/MC/X86/apx/popcnt-att.s b/llvm/test/MC/X86/apx/popcnt-att.s
new file mode 100644
index 0000000000000..a25c27cc3a1b2
--- /dev/null
+++ b/llvm/test/MC/X86/apx/popcnt-att.s
@@ -0,0 +1,38 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+# CHECK: {evex}	popcntw	%dx, %ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0x88,0xc2]
+         {evex}	popcntw	%dx, %ax
+# CHECK: {nf}	popcntw	%dx, %ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0x88,0xc2]
+         {nf}	popcntw	%dx, %ax
+# CHECK: {evex}	popcntl	%ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0x88,0xd1]
+         {evex}	popcntl	%ecx, %edx
+# CHECK: {nf}	popcntl	%ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0x88,0xd1]
+         {nf}	popcntl	%ecx, %edx
+# CHECK: {evex}	popcntq	%r9, %r15
+# CHECK: encoding: [0x62,0x54,0xfc,0x08,0x88,0xf9]
+         {evex}	popcntq	%r9, %r15
+# CHECK: {nf}	popcntq	%r9, %r15
+# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0x88,0xf9]
+         {nf}	popcntq	%r9, %r15...
[truncated]

KanRobert
KanRobert approved these changes Jan 30, 2024
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LGTM

@KanRobert KanRobert merged commit d9e875d into llvm:main Jan 31, 2024
KanRobert added a commit that referenced this pull request Feb 1, 2024
@KanRobert
[X86][CodeGen] Set mayLoad = 1 for LZCNT/POPCNT/TZCNTrm_(EVEX|NF)
1395e58 
Promoted and NF LZCNT/POPCNT/TZCNT were supported in #79954.
B/c null_frag is used in the patterns for these variants, tablgen can
not infer mayLoad = 1 for them.

This can be tested by MCA tests, which will be added after
-mcpu=<cpu_with_apx> is supported.
carlosgalvezp pushed a commit to carlosgalvezp/llvm-project that referenced this pull request Feb 1, 2024
@KanRobert
[X86][CodeGen] Set mayLoad = 1 for LZCNT/POPCNT/TZCNTrm_(EVEX|NF)
a141e1a 
Promoted and NF LZCNT/POPCNT/TZCNT were supported in llvm#79954.
B/c null_frag is used in the patterns for these variants, tablgen can
not infer mayLoad = 1 for them.

This can be tested by MCA tests, which will be added after
-mcpu=<cpu_with_apx> is supported.
agozillon pushed a commit to agozillon/llvm-project that referenced this pull request Feb 5, 2024
@KanRobert @agozillon
[X86][CodeGen] Set mayLoad = 1 for LZCNT/POPCNT/TZCNTrm_(EVEX|NF)
977d232 
Promoted and NF LZCNT/POPCNT/TZCNT were supported in llvm#79954.
B/c null_frag is used in the patterns for these variants, tablgen can
not infer mayLoad = 1 for them.

This can be tested by MCA tests, which will be added after
-mcpu=<cpu_with_apx> is supported.
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@KanRobert KanRobert KanRobert approved these changes

@phoebewang phoebewang Awaiting requested review from phoebewang

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@XinWang10 @llvmbot @KanRobert