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[RISCV][ISel] Add codegen support for the experimental zabha extension #80192

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Merged
merged 5 commits into from
Feb 16, 2024
Merged

[RISCV][ISel] Add codegen support for the experimental zabha extension #80192

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0f25140
[RISCV][ISel] Add codegen support for the experimental zabha extension
dtcxzyw Feb 1, 2024
6f46d0c
Merge remote-tracking branch 'origin/main' into HEAD
topperc Feb 9, 2024
94f6a6a
Update after #80947. Address review comments.
topperc Feb 10, 2024
fa01dcc
Merge branch 'main' into zabha-codegen-support
dtcxzyw Feb 14, 2024
2e0e1a2
fixup! Update after #80947. Address review comments.
dtcxzyw Feb 14, 2024
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2 changes: 1 addition & 1 deletion llvm/docs/RISCVUsage.rst
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Expand Up @@ -250,7 +250,7 @@ The primary goal of experimental support is to assist in the process of ratifica
LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1>`_.

``experimental-zabha``
LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-zabha/tree/v1.0-rc1>`__.
LLVM implements the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-zabha/tree/v1.0-rc1>`__.

``experimental-zacas``
LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`__.
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2 changes: 1 addition & 1 deletion llvm/docs/ReleaseNotes.rst
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Expand Up @@ -94,7 +94,7 @@ Changes to the PowerPC Backend
Changes to the RISC-V Backend
-----------------------------

* Added assembler/disassembler support for the experimental Zabha (Byte and
* Added full support for the experimental Zabha (Byte and
Halfword Atomic Memory Operations) extension.
* Added assembler/disassembler support for the experimenatl Zalasr
(Load-Acquire and Store-Release) extension.
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22 changes: 15 additions & 7 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -641,7 +641,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,

if (Subtarget.hasStdExtA()) {
setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
setMinCmpXchgSizeInBits(32);
if (Subtarget.hasStdExtZabha() && Subtarget.hasStdExtZacas())
setMinCmpXchgSizeInBits(8);
else
setMinCmpXchgSizeInBits(32);
} else if (Subtarget.hasForcedAtomics()) {
setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
} else {
Expand Down Expand Up @@ -19690,12 +19693,16 @@ RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
return AtomicExpansionKind::None;

unsigned Size = AI->getType()->getPrimitiveSizeInBits();
if (Size == 8 || Size == 16)
return AtomicExpansionKind::MaskedIntrinsic;
if (AI->getOperation() == AtomicRMWInst::Nand) {
if (Subtarget.hasStdExtZacas() &&
(Size >= 32 || Subtarget.hasStdExtZabha()))
return AtomicExpansionKind::CmpXChg;
if (Size < 32)
return AtomicExpansionKind::MaskedIntrinsic;
}

if (Subtarget.hasStdExtZacas() && AI->getOperation() == AtomicRMWInst::Nand &&
(Size == Subtarget.getXLen() || Size == 32))
return AtomicExpansionKind::CmpXChg;
if (Size < 32 && !Subtarget.hasStdExtZabha())
return AtomicExpansionKind::MaskedIntrinsic;

return AtomicExpansionKind::None;
}
Expand Down Expand Up @@ -19818,7 +19825,8 @@ RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(
return AtomicExpansionKind::None;

unsigned Size = CI->getCompareOperand()->getType()->getPrimitiveSizeInBits();
if (Size == 8 || Size == 16)
if (!(Subtarget.hasStdExtZabha() && Subtarget.hasStdExtZacas()) &&
(Size == 8 || Size == 16))
return AtomicExpansionKind::MaskedIntrinsic;
return AtomicExpansionKind::None;
}
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27 changes: 27 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
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Expand Up @@ -185,3 +185,30 @@ let Predicates = [HasStdExtZabha, HasStdExtZacas] in {
defm AMOCAS_B : AMO_cas_aq_rl<0b00101, 0b000, "amocas.b", GPR>;
defm AMOCAS_H : AMO_cas_aq_rl<0b00101, 0b001, "amocas.h", GPR>;
}

/// AMOs

defm : AMOPat<"atomic_swap_8", "AMOSWAP_B", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_add_8", "AMOADD_B", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_and_8", "AMOAND_B", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_or_8", "AMOOR_B", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_xor_8", "AMOXOR_B", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_max_8", "AMOMAX_B", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_min_8", "AMOMIN_B", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_umax_8", "AMOMAXU_B", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_umin_8", "AMOMINU_B", XLenVT, [HasStdExtZabha]>;

defm : AMOPat<"atomic_swap_16", "AMOSWAP_H", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_add_16", "AMOADD_H", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_and_16", "AMOAND_H", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_or_16", "AMOOR_H", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_xor_16", "AMOXOR_H", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_max_16", "AMOMAX_H", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_min_16", "AMOMIN_H", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_umax_16", "AMOMAXU_H", XLenVT, [HasStdExtZabha]>;
defm : AMOPat<"atomic_load_umin_16", "AMOMINU_H", XLenVT, [HasStdExtZabha]>;

/// AMOCAS

defm : AMOCASPat<"atomic_cmp_swap_8", "AMOCAS_B", XLenVT, [HasStdExtZabha]>;
defm : AMOCASPat<"atomic_cmp_swap_16", "AMOCAS_H", XLenVT, [HasStdExtZabha]>;
22 changes: 22 additions & 0 deletions llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
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Expand Up @@ -7,6 +7,8 @@
; RUN: | FileCheck -check-prefixes=NOZACAS,RV64IA %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=ZACAS,RV64IA-ZACAS %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas,+experimental-zabha -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=ZACAS,RV64IA-ZABHA %s

; Test cmpxchg followed by a branch on the cmpxchg success value to see if the
; branch is folded into the cmpxchg expansion.
Expand Down Expand Up @@ -209,6 +211,16 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v
; RV64IA-ZACAS-NEXT: # %bb.5: # %do_cmpxchg
; RV64IA-ZACAS-NEXT: # %bb.2: # %exit
; RV64IA-ZACAS-NEXT: ret
;
; RV64IA-ZABHA-LABEL: cmpxchg_masked_and_branch1:
; RV64IA-ZABHA: # %bb.0: # %entry
; RV64IA-ZABHA-NEXT: .LBB2_1: # %do_cmpxchg
; RV64IA-ZABHA-NEXT: # =>This Inner Loop Header: Depth=1
; RV64IA-ZABHA-NEXT: mv a3, a1
; RV64IA-ZABHA-NEXT: amocas.b.aqrl a3, a2, (a0)
; RV64IA-ZABHA-NEXT: bne a3, a1, .LBB2_1
; RV64IA-ZABHA-NEXT: # %bb.2: # %exit
; RV64IA-ZABHA-NEXT: ret
entry:
br label %do_cmpxchg
do_cmpxchg:
Expand Down Expand Up @@ -351,6 +363,16 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v
; RV64IA-ZACAS-NEXT: beq a1, a4, .LBB3_1
; RV64IA-ZACAS-NEXT: # %bb.2: # %exit
; RV64IA-ZACAS-NEXT: ret
;
; RV64IA-ZABHA-LABEL: cmpxchg_masked_and_branch2:
; RV64IA-ZABHA: # %bb.0: # %entry
; RV64IA-ZABHA-NEXT: .LBB3_1: # %do_cmpxchg
; RV64IA-ZABHA-NEXT: # =>This Inner Loop Header: Depth=1
; RV64IA-ZABHA-NEXT: mv a3, a1
; RV64IA-ZABHA-NEXT: amocas.b.aqrl a3, a2, (a0)
; RV64IA-ZABHA-NEXT: beq a3, a1, .LBB3_1
; RV64IA-ZABHA-NEXT: # %bb.2: # %exit
; RV64IA-ZABHA-NEXT: ret
entry:
br label %do_cmpxchg
do_cmpxchg:
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