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[SelectionDAG] Add computeKnownBits support for ISD::STEP_VECTOR #80452

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Merged
merged 6 commits into from
Feb 8, 2024
Merged

[SelectionDAG] Add computeKnownBits support for ISD::STEP_VECTOR #80452

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ff14dd1
Add tests where we should be able to know the lo or hi bits are zero
lukel97 Feb 2, 2024
bb72363
[SelectionDAG] Add computeKnownBits support for ISD::STEP_VECTOR
lukel97 Feb 2, 2024
40012cf
Check for overflow
lukel97 Feb 2, 2024
d472126
Check for overflow in the max num of elements too
lukel97 Feb 2, 2024
d35a5a2
Check the minimum num of elts doesn't overflow either.
lukel97 Feb 3, 2024
32daac9
Overflow flag actually gets cleared every call, so check it after eac…
lukel97 Feb 3, 2024
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27 changes: 27 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3110,6 +3110,33 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
}
break;
}
case ISD::STEP_VECTOR: {
const APInt &Step = Op.getConstantOperandAPInt(0);

if (Step.isPowerOf2())
Known.Zero.setLowBits(Step.logBase2());

const Function &F = getMachineFunction().getFunction();

if (!isUIntN(BitWidth, Op.getValueType().getVectorMinNumElements()))
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I think this might be off by 1. Only Op.getValueType().getVectorMinNumElements() - 1 needs to fit in the bitwidth.

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Err. nevermind we need it to fit to load it into the APInt.

break;
const APInt MinNumElts =
APInt(BitWidth, Op.getValueType().getVectorMinNumElements());

bool Overflow;
const APInt MaxNumElts = getVScaleRange(&F, BitWidth)
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Are fixed vector ISD::STEP_VECTOR allowed?

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I don't believe we construct them. SDAGBuilder doesn't, so unless we have something somewhere which combines to them, no.

However, good point. Unless we have an assert to that effect somewhere, we should handle them (via a bail out) here.

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Never mind, we have the assert in SelectionDAG::getNode

   assert(VT.isScalableVector() &&
           "STEP_VECTOR can only be used with scalable types");
    assert(OpOpcode == ISD::TargetConstant &&
           VT.getVectorElementType() == N1.getValueType() &&
           "Unexpected step operand");

.getUnsignedMax()
.umul_ov(MinNumElts, Overflow);
if (Overflow)
break;

const APInt MaxValue = (MaxNumElts - 1).umul_ov(Step, Overflow);
if (Overflow)
break;

Known.Zero.setHighBits(MaxValue.countl_zero());
break;
}
case ISD::BUILD_VECTOR:
assert(!Op.getValueType().isScalableVector());
// Collect the known bits that are shared by every demanded vector element.
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42 changes: 42 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/stepvector.ll
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Expand Up @@ -733,3 +733,45 @@ entry:
%3 = shl <vscale x 16 x i64> %2, %1
ret <vscale x 16 x i64> %3
}

; maximum step is 4 * 2 = 8, so maximum step value is 7, so hi 61 bits are known
; zero
define <vscale x 2 x i64> @hi_bits_known_zero() vscale_range(2, 4) {
; CHECK-LABEL: hi_bits_known_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret
%step = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
%and = and <vscale x 2 x i64> %step, shufflevector(<vscale x 2 x i64> insertelement(<vscale x 2 x i64> poison, i64 u0xfffffffffffffff8, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
ret <vscale x 2 x i64> %and
}

; the maximum step here overflows so don't set the known hi bits
define <vscale x 2 x i64> @hi_bits_known_zero_overflow() vscale_range(2, 4) {
; CHECK-LABEL: hi_bits_known_zero_overflow:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vmul.vx v8, v8, a0
; CHECK-NEXT: vand.vi v8, v8, -8
; CHECK-NEXT: ret
%step = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
%step.mul = mul <vscale x 2 x i64> %step, shufflevector(<vscale x 2 x i64> insertelement(<vscale x 2 x i64> poison, i64 u0xffffffffffffffff, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
%and = and <vscale x 2 x i64> %step.mul, shufflevector(<vscale x 2 x i64> insertelement(<vscale x 2 x i64> poison, i64 u0xfffffffffffffff8, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
ret <vscale x 2 x i64> %and
}

; step values are multiple of 8, so lo 3 bits are known zero
define <vscale x 2 x i64> @lo_bits_known_zero() {
; CHECK-LABEL: lo_bits_known_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: ret
%step = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
%step.mul = mul <vscale x 2 x i64> %step, shufflevector(<vscale x 2 x i64> insertelement(<vscale x 2 x i64> poison, i64 8, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
%and = and <vscale x 2 x i64> %step.mul, shufflevector(<vscale x 2 x i64> insertelement(<vscale x 2 x i64> poison, i64 7, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
ret <vscale x 2 x i64> %and
}