[RISCV] sifive-p670 uses SiFive7SchedModel #80612
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I collected numbers that show that the SiFive7SchedModel was better than using NoSchedModel. The sifive-p670 is not a SiFive7 processor, however we have a P600SchedModel in our downstream that has not been updated since before SchedWriteRes accounted for LMUL & SEW. I collected numbers that show that the SiFive7SchedModel outpreformed this old model as well. We intend to add the P600SchedModel in the future, once it has been revamped and causes sifive-p670 to outpreform in comparison to the SiFive7NModel.
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@llvm/pr-subscribers-backend-risc-v Author: Michael Maitland (michaelmaitland) ChangesI collected numbers that show that the SiFive7SchedModel was better than using NoSchedModel. The sifive-p670 is not a SiFive7 processor, however we have a P600SchedModel in our downstream that has not been updated since before SchedWriteRes accounted for LMUL & SEW. I collected numbers that show that the SiFive7SchedModel outpreformed this old model as well. We intend to add the P600SchedModel in the future, once it has been revamped and causes sifive-p670 to outpreform in comparison to the SiFive7NModel. Full diff: https://github.com/llvm/llvm-project/pull/80612.diff 1 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 59bb811058d48..79f62465b48fb 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -245,7 +245,7 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
TuneLUIADDIFusion,
TuneAUIPCADDIFusion]>;
-def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel,
+def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFive7Model,
[Feature64Bit,
FeatureStdExtZifencei,
FeatureStdExtM,
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How long will it take? We may don't need this intermediate solution if it will be soon. |
Not sure how long it will take. It is still in the backlog at the moment. Many measurements will need to be made. I am in support of this intermediate solution since the numbers put performance in the right direction and this is a pretty non-invasive change. |
…lvm#84962) This PR includes an initial scheduler model shows improvement on multiple workloads over NoSchedModel and SiFive7Model for sifive-p670. We plan on making significant changes to this model in the future so that it is more accurate. This patch would close llvm#80612.
I collected numbers that show that the SiFive7SchedModel was better than using NoSchedModel.
The sifive-p670 is not a SiFive7 processor, however we have a P600SchedModel in our downstream that has not been updated since before SchedWriteRes accounted for LMUL & SEW. I collected numbers that show that the SiFive7SchedModel outpreformed this old model as well.
We intend to add the P600SchedModel in the future, once it has been revamped and causes sifive-p670 to outpreform in comparison to the SiFive7NModel.