[RISCV][NFC] Use maybe_unused instead of casting to void to fix unused variable warning. #80651
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@llvm/pr-subscribers-backend-risc-v Author: Yeting Kuo (yetingk) ChangesFull diff: https://github.com/llvm/llvm-project/pull/80651.diff 7 Files Affected:
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index f6e8386aff451..4063719582bb9 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1222,8 +1222,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
int64_t Imm = 0;
if (Kind == KindTy::Immediate) {
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
- bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
- (void)IsConstantImm;
+ [[maybe_unused]] bool IsConstantImm =
+ evaluateConstantImm(getImm(), Imm, VK);
assert(IsConstantImm && "Invalid VTypeI Operand!");
} else {
Imm = getVType();
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 4dd039159e29d..f1ca1212ec378 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -380,8 +380,8 @@ static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
- DecodeStatus Result = DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
- (void)Result;
+ [[maybe_unused]] DecodeStatus Result =
+ DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
assert(Result == MCDisassembler::Success && "Invalid register");
Inst.addOperand(Inst.getOperand(0));
Inst.addOperand(MCOperand::createImm(0));
@@ -392,8 +392,8 @@ static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5);
- DecodeStatus Result = DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder);
- (void)Result;
+ [[maybe_unused]] DecodeStatus Result =
+ DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder);
assert(Result == MCDisassembler::Success && "Invalid register");
return MCDisassembler::Success;
}
@@ -404,8 +404,8 @@ static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
Inst.addOperand(MCOperand::createReg(RISCV::X0));
uint32_t SImm6 =
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
- DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
- (void)Result;
+ [[maybe_unused]] DecodeStatus Result =
+ decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
assert(Result == MCDisassembler::Success && "Invalid immediate");
return MCDisassembler::Success;
}
@@ -417,8 +417,8 @@ static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
Inst.addOperand(Inst.getOperand(0));
uint32_t UImm6 =
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
- DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
- (void)Result;
+ [[maybe_unused]] DecodeStatus Result =
+ decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
assert(Result == MCDisassembler::Success && "Invalid immediate");
return MCDisassembler::Success;
}
@@ -454,8 +454,8 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder);
DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder);
DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
- DecodeStatus Result = decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
- (void)Result;
+ [[maybe_unused]] DecodeStatus Result =
+ decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
assert(Result == MCDisassembler::Success && "Invalid immediate");
// Disassemble the final operand which is implicit.
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index bd49875c9591d..182a9c1544fd2 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -186,9 +186,8 @@ void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
case RISCV::C_BNEZ:
case RISCV::C_J:
case RISCV::C_JAL: {
- bool Success = RISCVRVC::uncompress(Res, Inst, STI);
+ [[maybe_unused]] bool Success = RISCVRVC::uncompress(Res, Inst, STI);
assert(Success && "Can't uncompress instruction");
- (void)Success;
break;
}
case RISCV::BEQ:
@@ -218,9 +217,9 @@ bool RISCVAsmBackend::relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF,
size_t OldSize = Data.size();
int64_t Value;
- bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
+ [[maybe_unused]] bool IsAbsolute =
+ AddrDelta.evaluateKnownAbsolute(Value, Layout);
assert(IsAbsolute && "CFA with invalid expression");
- (void)IsAbsolute;
Data.clear();
Fixups.clear();
@@ -283,9 +282,9 @@ bool RISCVAsmBackend::relaxDwarfCFA(MCDwarfCallFrameFragment &DF,
int64_t Value;
if (AddrDelta.evaluateAsAbsolute(Value, Layout.getAssembler()))
return false;
- bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
+ [[maybe_unused]] bool IsAbsolute =
+ AddrDelta.evaluateKnownAbsolute(Value, Layout);
assert(IsAbsolute && "CFA with invalid expression");
- (void)IsAbsolute;
Data.clear();
Fixups.clear();
diff --git a/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp b/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp
index 6ee006525df56..271d28f86a670 100644
--- a/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp
@@ -146,7 +146,8 @@ bool RISCVFoldMasks::convertToUnmasked(MachineInstr &MI,
// everything else. See the comment on RISCVMaskedPseudo for details.
const unsigned Opc = I->UnmaskedPseudo;
const MCInstrDesc &MCID = TII->get(Opc);
- const bool HasPolicyOp = RISCVII::hasVecPolicyOp(MCID.TSFlags);
+ [[maybe_unused]] const bool HasPolicyOp =
+ RISCVII::hasVecPolicyOp(MCID.TSFlags);
const bool HasPassthru = RISCVII::isFirstDefTiedToFirstUse(MCID);
#ifndef NDEBUG
const MCInstrDesc &MaskedMCID = TII->get(MI.getOpcode());
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 48ca7b74384c6..80797e36ad40f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2081,10 +2081,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
break;
RISCVII::VLMUL SubVecLMUL = RISCVTargetLowering::getLMUL(SubVecContainerVT);
- bool IsSubVecPartReg = SubVecLMUL == RISCVII::VLMUL::LMUL_F2 ||
- SubVecLMUL == RISCVII::VLMUL::LMUL_F4 ||
- SubVecLMUL == RISCVII::VLMUL::LMUL_F8;
- (void)IsSubVecPartReg; // Silence unused variable warning without asserts.
+ [[maybe_unused]] bool IsSubVecPartReg =
+ SubVecLMUL == RISCVII::VLMUL::LMUL_F2 ||
+ SubVecLMUL == RISCVII::VLMUL::LMUL_F4 ||
+ SubVecLMUL == RISCVII::VLMUL::LMUL_F8;
assert((!IsSubVecPartReg || V.isUndef()) &&
"Expecting lowering to have created legal INSERT_SUBVECTORs when "
"the subvector is smaller than a full-sized register");
@@ -2263,9 +2263,8 @@ bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
case InlineAsm::ConstraintCode::o:
case InlineAsm::ConstraintCode::m: {
SDValue Op0, Op1;
- bool Found = SelectAddrRegImm(Op, Op0, Op1);
+ [[maybe_unused]] bool Found = SelectAddrRegImm(Op, Op0, Op1);
assert(Found && "SelectAddrRegImm should always succeed");
- (void)Found;
OutOps.push_back(Op0);
OutOps.push_back(Op1);
return false;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 9f501ea7425de..27037f4d5c5c8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8512,12 +8512,12 @@ static SDValue lowerGetVectorLength(SDNode *N, SelectionDAG &DAG,
// Determine the VF that corresponds to LMUL 1 for ElementWidth.
unsigned LMul1VF = RISCV::RVVBitsPerBlock / ElementWidth;
// We don't support VF==1 with ELEN==32.
- unsigned MinVF = RISCV::RVVBitsPerBlock / Subtarget.getELen();
+ [[maybe_unused]] unsigned MinVF =
+ RISCV::RVVBitsPerBlock / Subtarget.getELen();
- unsigned VF = N->getConstantOperandVal(2);
+ [[maybe_unused]] unsigned VF = N->getConstantOperandVal(2);
assert(VF >= MinVF && VF <= (LMul1VF * 8) && isPowerOf2_32(VF) &&
"Unexpected VF");
- (void)MinVF;
bool Fractional = VF < LMul1VF;
unsigned LMulVal = Fractional ? LMul1VF / VF : VF / LMul1VF;
@@ -11227,7 +11227,7 @@ SDValue RISCVTargetLowering::lowerMaskedGather(SDValue Op,
SDValue Chain = MemSD->getChain();
SDValue BasePtr = MemSD->getBasePtr();
- ISD::LoadExtType LoadExtType;
+ [[maybe_unused]] ISD::LoadExtType LoadExtType;
SDValue Index, Mask, PassThru, VL;
if (auto *VPGN = dyn_cast<VPGatherSDNode>(Op.getNode())) {
@@ -11255,7 +11255,6 @@ SDValue RISCVTargetLowering::lowerMaskedGather(SDValue Op,
// Targets have to explicitly opt-in for extending vector loads.
assert(LoadExtType == ISD::NON_EXTLOAD &&
"Unexpected extending MGATHER/VP_GATHER");
- (void)LoadExtType;
// If the mask is known to be all ones, optimize to an unmasked intrinsic;
// the selection of the masked intrinsics doesn't do this for us.
@@ -11325,7 +11324,7 @@ SDValue RISCVTargetLowering::lowerMaskedScatter(SDValue Op,
SDValue Chain = MemSD->getChain();
SDValue BasePtr = MemSD->getBasePtr();
- bool IsTruncatingStore = false;
+ [[maybe_unused]] bool IsTruncatingStore = false;
SDValue Index, Mask, Val, VL;
if (auto *VPSN = dyn_cast<VPScatterSDNode>(Op.getNode())) {
@@ -11354,7 +11353,6 @@ SDValue RISCVTargetLowering::lowerMaskedScatter(SDValue Op,
// Targets have to explicitly opt-in for extending vector loads and
// truncating vector stores.
assert(!IsTruncatingStore && "Unexpected truncating MSCATTER/VP_SCATTER");
- (void)IsTruncatingStore;
// If the mask is known to be all ones, optimize to an unmasked intrinsic;
// the selection of the masked intrinsics doesn't do this for us.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index df516d7cd5c09..89eb71d917428 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1172,7 +1172,6 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
SmallVector<MachineOperand, 3> Cond;
if (analyzeBranch(*MBB, TBB, FBB, Cond, /*AllowModify=*/false))
return false;
- (void)FBB;
RISCVCC::CondCode CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
assert(CC != RISCVCC::COND_INVALID);
|
asb
approved these changes
Feb 5, 2024
There was a problem hiding this comment.
Although the sample code in CodingStandards for silencing a warning from an unused var (which uses a cast) hasn't been updated, I see plenty of [[maybe_unused]] usage in the LLVM codebase and there seemed support for using it more broadly in a thread that died out. In the context of the RISC-V backend, this seems like a reasonable clean-up to me and it's small in scope. LGTM.
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