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[RISCV] Adjust a few vector scheduler class names. NFC #80795

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Merged
merged 1 commit into from
Feb 6, 2024
Merged

[RISCV] Adjust a few vector scheduler class names. NFC #80795

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8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVInstrInfoV.td
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Original file line number Diff line number Diff line change
Expand Up @@ -861,9 +861,9 @@ multiclass VMSFS_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
SchedUnaryMC<"WriteVMSFSV", "ReadVMSFSV">;
}

multiclass VMIOT_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
multiclass VIOTA_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>,
SchedUnaryMC<"WriteVMIotV", "ReadVMIotV">;
SchedUnaryMC<"WriteVIotaV", "ReadVIotaV">;
}

multiclass VSHT_IV_V_X_I<string opcodestr, bits<6> funct6> {
Expand Down Expand Up @@ -1621,7 +1621,7 @@ defm VMSIF_M : VMSFS_MV_V<"vmsif.m", 0b010100, 0b00011>;
// vmsof.m set-only-first mask bit
defm VMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010100, 0b00010>;
// Vector Iota Instruction
defm VIOTA_M : VMIOT_MV_V<"viota.m", 0b010100, 0b10000>;
defm VIOTA_M : VIOTA_MV_V<"viota.m", 0b010100, 0b10000>;

} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota

Expand All @@ -1631,7 +1631,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
let vs2 = 0 in
def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd),
(ins VMaskOp:$vm), "vid.v", "$vd$vm">,
SchedNullaryMC<"WriteVMIdxV">;
SchedNullaryMC<"WriteVIdxV">;

// Integer Scalar Move Instructions
let vm = 1, RVVConstraint = NoConstraint in {
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Expand Up @@ -2066,10 +2066,10 @@ multiclass VPseudoVID_V {
defvar mx = m.MX;
let VLMul = m.value in {
def "_V_" # mx : VPseudoNullaryNoMask<m.vrclass>,
SchedNullary<"WriteVMIdxV", mx, forceMergeOpRead=true>;
SchedNullary<"WriteVIdxV", mx, forceMergeOpRead=true>;
def "_V_" # mx # "_MASK" : VPseudoNullaryMask<m.vrclass>,
RISCVMaskedPseudo<MaskIdx=1>,
SchedNullary<"WriteVMIdxV", mx,
SchedNullary<"WriteVIdxV", mx,
forceMergeOpRead=true>;
}
}
Expand All @@ -2084,17 +2084,17 @@ multiclass VPseudoNullaryPseudoM <string BaseInst> {
}
}

multiclass VPseudoVIOT_M {
multiclass VPseudoVIOTA_M {
defvar constraint = "@earlyclobber $rd";
foreach m = MxList in {
defvar mx = m.MX;
let VLMul = m.value in {
def "_" # mx : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,
SchedUnary<"WriteVMIotV", "ReadVMIotV", mx,
SchedUnary<"WriteVIotaV", "ReadVIotaV", mx,
forceMergeOpRead=true>;
def "_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,
RISCVMaskedPseudo<MaskIdx=2, MaskAffectsRes=true>,
SchedUnary<"WriteVMIotV", "ReadVMIotV", mx,
SchedUnary<"WriteVIotaV", "ReadVIotaV", mx,
forceMergeOpRead=true>;
}
}
Expand Down Expand Up @@ -6747,7 +6747,7 @@ defm PseudoVMSOF: VPseudoVSFS_M;
//===----------------------------------------------------------------------===//
// 15.8. Vector Iota Instruction
//===----------------------------------------------------------------------===//
defm PseudoVIOTA_M: VPseudoVIOT_M;
defm PseudoVIOTA_M: VPseudoVIOTA_M;

//===----------------------------------------------------------------------===//
// 15.9. Vector Element Index Instruction
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
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Expand Up @@ -868,8 +868,8 @@ foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
defm "" : LMULWriteResMX<"WriteVMIotV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVMIdxV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIotaV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIdxV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
}
}

Expand Down Expand Up @@ -1173,7 +1173,7 @@ defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
defm "" : LMULReadAdvance<"ReadVIotaV", 0>;

// 17. Vector Permutation Instructions
def : ReadAdvance<ReadVIMovVX, 0>;
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/RISCV/RISCVScheduleV.td
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Expand Up @@ -473,9 +473,9 @@ defm "" : LMULSchedWrites<"WriteVMFFSV">;
// 15.6. Vector Set-only-First Mask Bit
defm "" : LMULSchedWrites<"WriteVMSFSV">;
// 15.8. Vector Iota Instruction
defm "" : LMULSchedWrites<"WriteVMIotV">;
defm "" : LMULSchedWrites<"WriteVIotaV">;
// 15.9. Vector Element Index Instruction
defm "" : LMULSchedWrites<"WriteVMIdxV">;
defm "" : LMULSchedWrites<"WriteVIdxV">;

// 16. Vector Permutation Instructions
// 16.1. Integer Scalar Move Instructions
Expand Down Expand Up @@ -700,7 +700,7 @@ defm "" : LMULSchedReads<"ReadVMFFSV">;
// 15.6. Vector Set-only-First Mask Bit
defm "" : LMULSchedReads<"ReadVMSFSV">;
// 15.8. Vector Iota Instruction
defm "" : LMULSchedReads<"ReadVMIotV">;
defm "" : LMULSchedReads<"ReadVIotaV">;

// 16. Vector Permutation Instructions
// 16.1. Integer Scalar Move Instructions
Expand Down Expand Up @@ -912,8 +912,8 @@ defm "" : LMULWriteRes<"WriteVMALUV", []>;
defm "" : LMULWriteRes<"WriteVMPopV", []>;
defm "" : LMULWriteRes<"WriteVMFFSV", []>;
defm "" : LMULWriteRes<"WriteVMSFSV", []>;
defm "" : LMULWriteRes<"WriteVMIotV", []>;
defm "" : LMULWriteRes<"WriteVMIdxV", []>;
defm "" : LMULWriteRes<"WriteVIotaV", []>;
defm "" : LMULWriteRes<"WriteVIdxV", []>;

// 16. Vector Permutation Instructions
def : WriteRes<WriteVIMovVX, []>;
Expand Down Expand Up @@ -1074,7 +1074,7 @@ defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
defm "" : LMULReadAdvance<"ReadVIotaV", 0>;

// 16. Vector Permutation Instructions
def : ReadAdvance<ReadVIMovVX, 0>;
Expand Down