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[mlir][VectorOps] Add fold vector.shuffle -> vector.interleave (4/4) #80968

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42 changes: 41 additions & 1 deletion mlir/lib/Dialect/Vector/IR/VectorOps.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2479,11 +2479,51 @@ class ShuffleSplat final : public OpRewritePattern<ShuffleOp> {
}
};

/// Pattern to rewrite a fixed-size interleave via vector.shuffle to
/// vector.interleave.
class ShuffleInterleave : public OpRewritePattern<ShuffleOp> {
public:
using OpRewritePattern::OpRewritePattern;

LogicalResult matchAndRewrite(ShuffleOp op,
PatternRewriter &rewriter) const override {
VectorType resultType = op.getResultVectorType();
if (resultType.isScalable())
return rewriter.notifyMatchFailure(
op, "ShuffleOp can't represent a scalable interleave");
Comment on lines +2491 to +2493
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this case shouldn't be allowed by the verifier so I would replace this with an assert.

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There's currently no checks on vector.shuffle for scalable vectors 😔

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it would be better to add that to the verified


if (resultType.getRank() != 1)
return rewriter.notifyMatchFailure(
op, "ShuffleOp can't represent an n-D interleave");

VectorType sourceType = op.getV1VectorType();
if (sourceType != op.getV2VectorType() ||
Comment on lines +2499 to +2500
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Can shuffle inputs have different types?

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I don't think so. From the shuffle docs:

the two operands must have the same element type as the result

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I thought their shapes should also match. Anyways...

sourceType.getNumElements() * 2 != resultType.getNumElements()) {
return rewriter.notifyMatchFailure(
op, "ShuffleOp types don't match an interleave");
}

ArrayAttr shuffleMask = op.getMask();
int64_t resultVectorSize = resultType.getNumElements();
for (int i = 0, e = resultVectorSize / 2; i < e; ++i) {
int64_t maskValueA = cast<IntegerAttr>(shuffleMask[i * 2]).getInt();
int64_t maskValueB = cast<IntegerAttr>(shuffleMask[(i * 2) + 1]).getInt();
if (maskValueA != i || maskValueB != (resultVectorSize / 2) + i)
return rewriter.notifyMatchFailure(op,
"ShuffleOp mask not interleaving");
}

rewriter.replaceOpWithNewOp<InterleaveOp>(op, op.getV1(), op.getV2());
return success();
}
};

} // namespace

void ShuffleOp::getCanonicalizationPatterns(RewritePatternSet &results,
MLIRContext *context) {
results.add<ShuffleSplat, Canonicalize0DShuffleOp>(context);
results.add<ShuffleSplat, ShuffleInterleave, Canonicalize0DShuffleOp>(
context);
}

//===----------------------------------------------------------------------===//
Expand Down
23 changes: 23 additions & 0 deletions mlir/test/Dialect/Vector/canonicalize.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -2567,3 +2567,26 @@ func.func @load_store_forwarding_rank_mismatch(%v0: vector<4x1x1xf32>, %arg0: te
tensor<4x4x4xf32>, vector<1x100x4x5xf32>
return %r : vector<1x100x4x5xf32>
}

// -----

// CHECK-LABEL: func.func @rank_0_shuffle_to_interleave(
// CHECK-SAME: %[[LHS:.*]]: vector<f64>, %[[RHS:.*]]: vector<f64>)
func.func @rank_0_shuffle_to_interleave(%arg0: vector<f64>, %arg1: vector<f64>) -> vector<2xf64>
{
// CHECK: %[[ZIP:.*]] = vector.interleave %[[LHS]], %[[RHS]] : vector<f64>
// CHECK: return %[[ZIP]]
%0 = vector.shuffle %arg0, %arg1 [0, 1] : vector<f64>, vector<f64>
return %0 : vector<2xf64>
}

// -----

// CHECK-LABEL: func.func @rank_1_shuffle_to_interleave(
// CHECK-SAME: %[[LHS:.*]]: vector<6xi32>, %[[RHS:.*]]: vector<6xi32>)
func.func @rank_1_shuffle_to_interleave(%arg0: vector<6xi32>, %arg1: vector<6xi32>) -> vector<12xi32> {
// CHECK: %[[ZIP:.*]] = vector.interleave %[[LHS]], %[[RHS]] : vector<6xi32>
// CHECK: return %[[ZIP]]
%0 = vector.shuffle %arg0, %arg1 [0, 6, 1, 7, 2, 8, 3, 9, 4, 10, 5, 11] : vector<6xi32>, vector<6xi32>
return %0 : vector<12xi32>
}