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[mlir][ArmSVE] Add intrinsics for the SME2 multi-vector zips #80985

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Feb 9, 2024
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[mlir][ArmSVE] Add intrinsics for the SME2 multi-vector zips #80985

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25 changes: 23 additions & 2 deletions mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
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Original file line number Diff line number Diff line change
Expand Up @@ -59,14 +59,15 @@ class ArmSVE_Op<string mnemonic, list<Trait> traits = []> :
class ArmSVE_IntrOp<string mnemonic,
list<Trait> traits = [],
list<int> overloadedOperands = [],
list<int> overloadedResults = []> :
list<int> overloadedResults = [],
int numResults = 1> :
LLVM_IntrOpBase</*Dialect dialect=*/ArmSVE_Dialect,
/*string opName=*/"intr." # mnemonic,
/*string enumName=*/"aarch64_sve_" # !subst(".", "_", mnemonic),
/*list<int> overloadedResults=*/overloadedResults,
/*list<int> overloadedOperands=*/overloadedOperands,
/*list<Trait> traits=*/traits,
/*int numResults=*/1>;
/*int numResults=*/numResults>;

class ArmSVE_IntrBinaryOverloadedOp<string mnemonic,
list<Trait> traits = []>:
Expand Down Expand Up @@ -410,4 +411,24 @@ def ConvertToSvboolIntrOp :
/*overloadedResults=*/[]>,
Arguments<(ins SVEPredicate:$mask)>;

// Note: This multi-vector intrinsic requires SME2.
def ZipX2IntrOp : ArmSVE_IntrOp<"zip.x2",
/*traits=*/[],
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AllTypesMatch? (and for x4)

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All the SVE intrinsics are super lax like this. 'AnyScalableVector' is much more than these can actually take, I've left the type checking to the actual ops.

/*overloadedOperands=*/[0],
/*overloadedResults=*/[],
/*numResults=*/2>,
Arguments<(ins Arg<AnyScalableVector, "v1">:$v1,
Arg<AnyScalableVector, "v2">:$v2)>;

// Note: This multi-vector intrinsic requires SME2.
def ZipX4IntrOp : ArmSVE_IntrOp<"zip.x4",
/*traits=*/[],
/*overloadedOperands=*/[0],
/*overloadedResults=*/[],
/*numResults=*/4>,
Arguments<(ins Arg<AnyScalableVector, "v1">:$v1,
Arg<AnyScalableVector, "v2">:$v2,
Arg<AnyScalableVector, "v3">:$v3,
Arg<AnyScalableVector, "v3">:$v4)>;

#endif // ARMSVE_OPS
42 changes: 42 additions & 0 deletions mlir/test/Target/LLVMIR/arm-sve.mlir
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Expand Up @@ -314,3 +314,45 @@ llvm.func @arm_sve_convert_to_svbool(
: (vector<[1]xi1>) -> vector<[16]xi1>
llvm.return
}

// CHECK-LABEL: arm_sve_zip_x2(
// CHECK-SAME: <vscale x 16 x i8> %[[V1:[0-9]+]],
// CHECK-SAME: <vscale x 8 x i16> %[[V2:[0-9]+]],
// CHECK-SAME: <vscale x 4 x i32> %[[V3:[0-9]+]],
// CHECK-SAME: <vscale x 2 x i64> %[[V4:[0-9]+]])
llvm.func @arm_sve_zip_x2(%nxv16i8: vector<[16]xi8>, %nxv8i16: vector<[8]xi16>, %nxv4i32: vector<[4]xi32>, %nxv2i64: vector<[2]xi64>) {
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I guess these inputs are not required to match SVE register sizes?

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I think they are, but as with all the other SVE intrinsics (and most intrinsics in general) the checking is very minimal. The higher level arm_sve.zip.x4 and arm_sve.zip.x2 will more rigorously check types.

// CHECK: call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %[[V1]], <vscale x 16 x i8> %[[V1]])
%0 = "arm_sve.intr.zip.x2"(%nxv16i8, %nxv16i8) : (vector<[16]xi8>, vector<[16]xi8>)
-> !llvm.struct<(vector<[16]xi8>, vector<[16]xi8>)>
// CHECK: call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16> %[[V2]], <vscale x 8 x i16> %[[V2]])
%1 = "arm_sve.intr.zip.x2"(%nxv8i16, %nxv8i16) : (vector<[8]xi16>, vector<[8]xi16>)
-> !llvm.struct<(vector<[8]xi16>, vector<[8]xi16>)>
// CHECK: call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.zip.x2.nxv4i32(<vscale x 4 x i32> %[[V3]], <vscale x 4 x i32> %[[V3]])
%2 = "arm_sve.intr.zip.x2"(%nxv4i32, %nxv4i32) : (vector<[4]xi32>, vector<[4]xi32>)
-> !llvm.struct<(vector<[4]xi32>, vector<[4]xi32>)>
// CHECK: call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.zip.x2.nxv2i64(<vscale x 2 x i64> %[[V4]], <vscale x 2 x i64> %[[V4]])
%3 = "arm_sve.intr.zip.x2"(%nxv2i64, %nxv2i64) : (vector<[2]xi64>, vector<[2]xi64>)
-> !llvm.struct<(vector<[2]xi64>, vector<[2]xi64>)>
llvm.return
}

// CHECK-LABEL: arm_sve_zip_x4(
// CHECK-SAME: <vscale x 16 x i8> %[[V1:[0-9]+]],
// CHECK-SAME: <vscale x 8 x i16> %[[V2:[0-9]+]],
// CHECK-SAME: <vscale x 4 x i32> %[[V3:[0-9]+]],
// CHECK-SAME: <vscale x 2 x i64> %[[V4:[0-9]+]])
llvm.func @arm_sve_zip_x4(%nxv16i8: vector<[16]xi8>, %nxv8i16: vector<[8]xi16>, %nxv4i32: vector<[4]xi32>, %nxv2i64: vector<[2]xi64>) {
// CHECK: call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %[[V1]], <vscale x 16 x i8> %[[V1]], <vscale x 16 x i8> %[[V1]], <vscale x 16 x i8> %[[V1]])
%0 = "arm_sve.intr.zip.x4"(%nxv16i8, %nxv16i8, %nxv16i8, %nxv16i8) : (vector<[16]xi8>, vector<[16]xi8>, vector<[16]xi8>, vector<[16]xi8>)
-> !llvm.struct<(vector<[16]xi8>, vector<[16]xi8>, vector<[16]xi8>, vector<[16]xi8>)>
// CHECK: call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x4.nxv8i16(<vscale x 8 x i16> %[[V2]], <vscale x 8 x i16> %[[V2]], <vscale x 8 x i16> %[[V2]], <vscale x 8 x i16> %[[V2]])
%1 = "arm_sve.intr.zip.x4"(%nxv8i16, %nxv8i16, %nxv8i16, %nxv8i16) : (vector<[8]xi16>, vector<[8]xi16>, vector<[8]xi16>, vector<[8]xi16>)
-> !llvm.struct<(vector<[8]xi16>, vector<[8]xi16>, vector<[8]xi16>, vector<[8]xi16>)>
// CHECK: call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.zip.x4.nxv4i32(<vscale x 4 x i32> %[[V3]], <vscale x 4 x i32> %[[V3]], <vscale x 4 x i32> %[[V3]], <vscale x 4 x i32> %[[V3]])
%2 = "arm_sve.intr.zip.x4"(%nxv4i32, %nxv4i32, %nxv4i32, %nxv4i32) : (vector<[4]xi32>, vector<[4]xi32>, vector<[4]xi32>, vector<[4]xi32>)
-> !llvm.struct<(vector<[4]xi32>, vector<[4]xi32>, vector<[4]xi32>, vector<[4]xi32>)>
// CHECK: call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.zip.x4.nxv2i64(<vscale x 2 x i64> %[[V4]], <vscale x 2 x i64> %[[V4]], <vscale x 2 x i64> %[[V4]], <vscale x 2 x i64> %[[V4]])
%3 = "arm_sve.intr.zip.x4"(%nxv2i64, %nxv2i64, %nxv2i64, %nxv2i64) : (vector<[2]xi64>, vector<[2]xi64>, vector<[2]xi64>, vector<[2]xi64>)
-> !llvm.struct<(vector<[2]xi64>, vector<[2]xi64>, vector<[2]xi64>, vector<[2]xi64>)>
llvm.return
}