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[mlir][ArmSME][test] Unroll reduction dimension in multi-tile-matmul.mlir #81160

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Feb 12, 2024
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[mlir][ArmSME][test] Unroll reduction dimension in multi-tile-matmul.mlir #81160

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10 changes: 5 additions & 5 deletions mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir
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Expand Up @@ -73,14 +73,14 @@ module attributes {transform.with_named_sequence} {
%matmul = transform.structured.match ops{["linalg.matmul"]} in %module
: (!transform.any_op) -> !transform.any_op

// Step 1: Tile for size [8] x [8], which corresponds to (2 x SVLs) x (2 x SVLs),
// where SVLs is the number of 32-bit elements in a vector of SVL bits.
// This uses all four 32-bit SME virtual tiles.
%tiled_linalg_op, %loop_i, %loop_j, %loop_k = transform.structured.tile_using_for %matmul[[8], [8], 1]
// Step 1: Tile for size [8] x [8] (unrolled by 4), which corresponds to
// (2 x SVLs) x (2 x SVLs), where SVLs is the number of 32-bit elements in a
// vector of SVL bits. This uses all four 32-bit SME virtual tiles.
%tiled_linalg_op, %loop_i, %loop_j, %loop_k = transform.structured.tile_using_for %matmul[[8], [8], 4]
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IIUC, the K dims controls the number of SSVE regs that we would use here, right? And we need 4 regs per 1 K dim? So the possible max before spilling happens would be 8, right?

That's tangential to this PR - I'm just curious about the optimal set-up :)

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Yep, that's about right 👍

: (!transform.any_op) -> (!transform.any_op, !transform.op<"scf.for">, !transform.op<"scf.for">, !transform.op<"scf.for">)

// Step 2: Vectorize.
transform.structured.vectorize %tiled_linalg_op vector_sizes [[8], [8], 1]
transform.structured.vectorize %tiled_linalg_op vector_sizes [[8], [8], 4]
: !transform.any_op

// Step 3: Bufferize ahead of TransferReadDropUnitDimsPattern, which
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