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[GlobalISel] Constant-fold G_PTR_ADD with different type sizes #81473

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Merged
merged 4 commits into from
Feb 22, 2024
Merged

[GlobalISel] Constant-fold G_PTR_ADD with different type sizes #81473

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9f2996b
[GlobalISel] Constant-fold G_PTR_ADD with different type sizes
Pierre-vh Feb 12, 2024
392468e
fix zext
Pierre-vh Feb 12, 2024
1c2683a
fix case where C2 > C1
Pierre-vh Feb 12, 2024
92ca14b
sextOrTrunc
Pierre-vh Feb 12, 2024
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5 changes: 4 additions & 1 deletion llvm/lib/CodeGen/GlobalISel/Utils.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -660,8 +660,11 @@ std::optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode,
default:
break;
case TargetOpcode::G_ADD:
case TargetOpcode::G_PTR_ADD:
return C1 + C2;
case TargetOpcode::G_PTR_ADD:
// Types can be of different width here.
// Result needs to be the same width as C1, so trunc or sext C2.
return C1 + C2.sextOrTrunc(C1.getBitWidth());
case TargetOpcode::G_AND:
return C1 & C2;
case TargetOpcode::G_ASHR:
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40 changes: 40 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir
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@@ -0,0 +1,40 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

# Tries to emit a foldable G_PTR_ADD with (p1, s32) operands.
---
name: test_ptradd_crash__offset_smaller
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_ptradd_crash__offset_smaller
; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 12
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[C]](p1) :: (load (s32), addrspace 1)
; CHECK-NEXT: $sgpr0 = COPY [[LOAD]](s32)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
%1:_(p1) = G_CONSTANT i64 0
%3:_(s32) = G_CONSTANT i32 3
%0:_(<4 x s32>) = G_LOAD %1 :: (load (<4 x s32>) from `ptr addrspace(1) null`, addrspace 1)
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %3
$sgpr0 = COPY %2
SI_RETURN_TO_EPILOG implicit $sgpr0
...

# Tries to emit a foldable G_PTR_ADD with (p1, s128) operands.
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Does this actually succeed in creating G_PTR_ADD with s128 RHS? If not, maybe it would be better to enforce in MachineVerifier that the RHS is no wider than the LHS?

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It should, MachineVerifier doesn't check for it + MachineIRBuilder doesn't complain

I can make a follow-up patch to enforce RHS <= LHS if you want

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No strong opinion. If we do anything, maybe we should enforce that the RHS has to be the width of the index size for the address space.

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If we do anything, maybe we should enforce that the RHS has to be the width of the index size for the address space.

#84352

---
name: test_ptradd_crash__offset_wider
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_ptradd_crash__offset_wider
; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 12
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[C]](p1) :: (load (s32), addrspace 1)
; CHECK-NEXT: $sgpr0 = COPY [[LOAD]](s32)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
%1:_(p1) = G_CONSTANT i64 0
%3:_(s128) = G_CONSTANT i128 3
%0:_(<4 x s32>) = G_LOAD %1 :: (load (<4 x s32>) from `ptr addrspace(1) null`, addrspace 1)
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %3
$sgpr0 = COPY %2
SI_RETURN_TO_EPILOG implicit $sgpr0
...