AMDGPU/NFC: Remove some bits from TSFlags #81525
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kzhuravl
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Feb 12, 2024
kzhuravl
commented
- AMDGPU/NFC: Purge SOPK_ZEXT from TSFlags
- Moved to helper function in SIInstInfo
- AMDGPU/NFC: Purge VOPAsmPrefer32Bit from TSFlags
- This flag did not make sense / remnants of something else I think
kzhuravl
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@llvm/pr-subscribers-backend-amdgpu Author: Konstantin Zhuravlyov (kzhuravl) Changes
Full diff: https://github.com/llvm/llvm-project/pull/81525.diff 9 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index a94da992b33859..79ad6ddf7861fc 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -3299,11 +3299,6 @@ unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
(isForcedSDWA() && !(TSFlags & SIInstrFlags::SDWA)) )
return Match_InvalidOperand;
- if ((TSFlags & SIInstrFlags::VOP3) &&
- (TSFlags & SIInstrFlags::VOPAsmPrefer32Bit) &&
- getForcedEncodingSize() != 64)
- return Match_PreferE32;
-
if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi ||
Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {
// v_mac_f32/16 allow only dst_sel == DWORD;
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 19596d53b45328..ca6728cf3ddc67 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -105,10 +105,16 @@ enum : uint64_t {
WQM = UINT64_C(1) << 35,
DisableWQM = UINT64_C(1) << 36,
Gather4 = UINT64_C(1) << 37,
- SOPK_ZEXT = UINT64_C(1) << 38,
+
+ // Reserved, must be 0.
+ Reserved0 = UINT64_C(1) << 38,
+
SCALAR_STORE = UINT64_C(1) << 39,
FIXED_SIZE = UINT64_C(1) << 40,
- VOPAsmPrefer32Bit = UINT64_C(1) << 41,
+
+ // Reserved, must be 0.
+ Reserved1 = UINT64_C(1) << 41,
+
VOP3_OPSEL = UINT64_C(1) << 42,
maybeAtomic = UINT64_C(1) << 43,
renamedInGFX9 = UINT64_C(1) << 44,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
index ab536f8f49d537..bdefcae278efa9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
@@ -69,10 +69,6 @@ class InstSI <dag outs, dag ins, string asm = "",
field bit Gather4 = 0;
- // Most sopk treat the immediate as a signed 16-bit, however some
- // use it as unsigned.
- field bit SOPKZext = 0;
-
// This is an s_store_dword* instruction that requires a cache flush
// on wave termination. It is necessary to distinguish from mayStore
// SMEM instructions like the cache flush ones.
@@ -82,10 +78,6 @@ class InstSI <dag outs, dag ins, string asm = "",
// instruction size.
field bit FixedSize = 0;
- // This bit tells the assembler to use the 32-bit encoding in case it
- // is unable to infer the encoding from the operands.
- field bit VOPAsmPrefer32Bit = 0;
-
// This bit indicates that this is a VOP3 opcode which supports op_sel
// modifier.
field bit VOP3_OPSEL = 0;
@@ -209,10 +201,15 @@ class InstSI <dag outs, dag ins, string asm = "",
let TSFlags{36} = DisableWQM;
let TSFlags{37} = Gather4;
- let TSFlags{38} = SOPKZext;
+ // Reserved, must be 0.
+ let TSFlags{38} = 0;
+
let TSFlags{39} = ScalarStore;
let TSFlags{40} = FixedSize;
- let TSFlags{41} = VOPAsmPrefer32Bit;
+
+ // Reserved, must be 0.
+ let TSFlags{41} = 0;
+
let TSFlags{42} = VOP3_OPSEL;
let TSFlags{43} = maybeAtomic;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c7628bd354309c..f5ec831234f2f9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4918,7 +4918,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
}
} else {
uint64_t Imm = Op->getImm();
- if (sopkIsZext(MI)) {
+ if (sopkIsZext(Opcode)) {
if (!isUInt<16>(Imm)) {
ErrInfo = "invalid immediate for SOPK instruction";
return false;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 2838a5c0791ff2..51df7897f8fde1 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -842,12 +842,16 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
}
- static bool sopkIsZext(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
- }
-
- bool sopkIsZext(uint16_t Opcode) const {
- return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
+ // Most sopk treat the immediate as a signed 16-bit, however some
+ // use it as unsigned.
+ static bool sopkIsZext(unsigned Opcode) {
+ return Opcode == AMDGPU::S_CMPK_EQ_U32 ||
+ Opcode == AMDGPU::S_CMPK_LG_U32 ||
+ Opcode == AMDGPU::S_CMPK_GT_U32 ||
+ Opcode == AMDGPU::S_CMPK_GE_U32 ||
+ Opcode == AMDGPU::S_CMPK_LT_U32 ||
+ Opcode == AMDGPU::S_CMPK_LE_U32 ||
+ Opcode == AMDGPU:: S_GETREG_B32;
}
/// \returns true if this is an s_store_dword* instruction. This is more
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index d290dd82b76058..3c6f6ddfd89d0d 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -251,9 +251,9 @@ void SIShrinkInstructions::shrinkScalarCompare(MachineInstr &MI) const {
const MCInstrDesc &NewDesc = TII->get(SOPKOpc);
- if ((TII->sopkIsZext(SOPKOpc) && isKUImmOperand(Src1)) ||
- (!TII->sopkIsZext(SOPKOpc) && isKImmOperand(Src1))) {
- if (!TII->sopkIsZext(SOPKOpc))
+ if ((SIInstrInfo::sopkIsZext(SOPKOpc) && isKUImmOperand(Src1)) ||
+ (!SIInstrInfo::sopkIsZext(SOPKOpc) && isKImmOperand(Src1))) {
+ if (!SIInstrInfo::sopkIsZext(SOPKOpc))
Src1.setImm(SignExtend64(Src1.getImm(), 32));
MI.setDesc(NewDesc);
}
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index c8e8ad2034dc98..d4c0c9f96496bb 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1078,14 +1078,12 @@ def S_CMPK_GE_I32 : SOPK_SCC <"s_cmpk_ge_i32", "s_cmp_ge_i32", 1>;
def S_CMPK_LT_I32 : SOPK_SCC <"s_cmpk_lt_i32", "s_cmp_lt_i32", 1>;
def S_CMPK_LE_I32 : SOPK_SCC <"s_cmpk_le_i32", "s_cmp_le_i32", 1>;
-let SOPKZext = 1 in {
def S_CMPK_EQ_U32 : SOPK_SCC <"s_cmpk_eq_u32", "s_cmp_eq_u32", 0>;
def S_CMPK_LG_U32 : SOPK_SCC <"s_cmpk_lg_u32", "s_cmp_lg_u32", 0>;
def S_CMPK_GT_U32 : SOPK_SCC <"s_cmpk_gt_u32", "s_cmp_gt_u32", 0>;
def S_CMPK_GE_U32 : SOPK_SCC <"s_cmpk_ge_u32", "s_cmp_ge_u32", 0>;
def S_CMPK_LT_U32 : SOPK_SCC <"s_cmpk_lt_u32", "s_cmp_lt_u32", 0>;
def S_CMPK_LE_U32 : SOPK_SCC <"s_cmpk_le_u32", "s_cmp_le_u32", 0>;
-} // End SOPKZext = 1
} // End isCompare = 1
let isCommutable = 1, DisableEncoding = "$src0",
@@ -1111,7 +1109,6 @@ def S_GETREG_B32 : SOPK_Pseudo <
(outs SReg_32:$sdst), (ins hwreg:$simm16),
"$sdst, $simm16",
[(set i32:$sdst, (int_amdgcn_s_getreg (i32 timm:$simm16)))]> {
- let SOPKZext = 1;
let hasSideEffects = 1;
}
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 58b67b21e274b5..41a03bb1e73c96 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -217,9 +217,7 @@ def VOP_I16_F16_SPECIAL_OMOD_t16 : VOPProfile_Fake16<VOP_I16_F16> {
// VOP1 Instructions
//===----------------------------------------------------------------------===//
-let VOPAsmPrefer32Bit = 1 in {
defm V_NOP : VOP1Inst <"v_nop", VOP_NOP_PROFILE>;
-}
def VOPProfile_MOV : VOPProfile <[i32, i32, untyped, untyped]> {
let InsVOPDX = (ins Src0RC32:$src0X);
@@ -368,9 +366,7 @@ defm V_FREXP_EXP_I32_F32 : VOP1Inst <"v_frexp_exp_i32_f32", VOP_I32_F32, int_amd
defm V_FREXP_MANT_F32 : VOP1Inst <"v_frexp_mant_f32", VOP_F32_F32, int_amdgcn_frexp_mant>;
} // End isReMaterializable = 1
-let VOPAsmPrefer32Bit = 1 in {
defm V_CLREXCP : VOP1Inst <"v_clrexcp", VOP_NO_EXT<VOP_NONE>>;
-}
// Restrict src0 to be VGPR
def VOP_MOVRELS : VOPProfile<[i32, i32, untyped, untyped]> {
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index 20d7c88fb7e59f..ea6df5f4049dff 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -16,7 +16,6 @@ class LetDummies {
bit isMoveImm;
bit isReMaterializable;
bit isAsCheapAsAMove;
- bit VOPAsmPrefer32Bit;
bit FPDPRounding;
Predicate SubtargetPredicate;
string Constraints;
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CRobeck
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Feb 16, 2024
…81901) Follow on to #81525 in the series of consolidating bits in TSFlags. Merge SGPRSpill and VGPRSpill into single Spill bit Modify isSGPRSpill and isVGPRSpill helper functions to differentiate VGPR and SGPR spills: Spill+SALU=SGPR Spill Spill+VALU=VGPR Spill The only exception here is SGPR spills to VGPRs which require an explicit instruction check.
CRobeck
added a commit
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Sep 26, 2024
…ion/macro to free up a bit slot (#82787) Follow on to #81525 and #81901 in the series of consolidating bits in TSFlags. Remove renamedInGFX9 from SIInstrFormats.td and move to helper function/macro in SIInstrInfo. renamedInGFX9 points to V_{add, sub, subrev, addc, subb, subbrev}_ U32 and V_{div_fixup_F16, fma_F16, interp_p2_F16, mad_F16, mad_U16, mad_I16}.
Sterling-Augustine
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that referenced
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Sep 27, 2024
…ion/macro to free up a bit slot (llvm#82787) Follow on to llvm#81525 and llvm#81901 in the series of consolidating bits in TSFlags. Remove renamedInGFX9 from SIInstrFormats.td and move to helper function/macro in SIInstrInfo. renamedInGFX9 points to V_{add, sub, subrev, addc, subb, subbrev}_ U32 and V_{div_fixup_F16, fma_F16, interp_p2_F16, mad_F16, mad_U16, mad_I16}.
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