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[X86][GlobalISel] Enable G_SDIV/G_UDIV/G_SREM/G_UREM #81615

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Merged
merged 6 commits into from
Mar 7, 2024
Merged

[X86][GlobalISel] Enable G_SDIV/G_UDIV/G_SREM/G_UREM #81615

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82c4e50
[X86][GlobalISel] Enable G_SDIV/G_UDIV/G_SREM/G_UREM
e-kud Feb 13, 2024
aec6cd2
Unify MIR legalizer tests
e-kud Feb 19, 2024
30d4578
Merge remote-tracking branch 'origin/main' into global-div-rem
e-kud Feb 29, 2024
07459c4
Remove alignment and registers from mir tests
e-kud Feb 29, 2024
f871f65
Drop IR from mir tests
e-kud Feb 29, 2024
e0c884c
Merge branch 'main' into global-div-rem
e-kud Mar 7, 2024
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9 changes: 3 additions & 6 deletions llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1778,12 +1778,9 @@ bool X86InstructionSelector::selectMulDivRem(MachineInstr &I,
.addImm(8);
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Probably for another patch, but we should match SelectionDAG here and use a MOVZX_NOREX or MOVSX_NOREX from AH here.

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Do you mean to replace COPY + SHR by movzx %ah, %ax?

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Yes this is the code from X86ISelDAGToDAG.cpp

    if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) {                     
      SDValue AHCopy = CurDAG->getRegister(X86::AH, MVT::i8);                    
      unsigned AHExtOpcode =                                                     
          isSigned ? X86::MOVSX32rr8_NOREX : X86::MOVZX32rr8_NOREX;              
                                                                                 
      SDNode *RNode = CurDAG->getMachineNode(AHExtOpcode, dl, MVT::i32,          
                                             MVT::Glue, AHCopy, InGlue);         
      SDValue Result(RNode, 0);                                                  
      InGlue = SDValue(RNode, 1);                                                
                                                                                 
      Result =                                                                   
          CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result);    
                                                                                 
      ReplaceUses(SDValue(Node, 1), Result);                                     
      LLVM_DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG);                
                 dbgs() << '\n');                                                
    }


// Now reference the 8-bit subreg of the result.
BuildMI(*I.getParent(), I, I.getDebugLoc(),
TII.get(TargetOpcode::SUBREG_TO_REG))
.addDef(DstReg)
.addImm(0)
.addReg(ResultSuperReg)
.addImm(X86::sub_8bit);
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
DstReg)
.addReg(ResultSuperReg, 0, X86::sub_8bit);
} else {
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
DstReg)
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1 change: 1 addition & 0 deletions llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
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Expand Up @@ -213,6 +213,7 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
return typeInSet(0, {s8, s16, s32})(Query) ||
(Is64Bit && typeInSet(0, {s64})(Query));
})
.libcallFor({s64})
.clampScalar(0, s8, sMaxScalar);

// integer shifts
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127 changes: 127 additions & 0 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-sdiv.mir
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@@ -0,0 +1,127 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,X64
# RUN: llc -mtriple=i686-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,X86

...
---
name: test_sdiv_i8
tracksRegLiveness: true
body: |
bb.1:
liveins: $edi, $esi

; CHECK-LABEL: name: test_sdiv_i8
; CHECK: liveins: $edi, $esi
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: $al = COPY [[SDIV]](s8)
; CHECK-NEXT: RET 0, implicit $al
%2:_(s32) = COPY $edi
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $esi
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SDIV %0, %1
$al = COPY %4(s8)
RET 0, implicit $al

...
---
name: test_sdiv_i16
tracksRegLiveness: true
body: |
bb.1:
liveins: $edi, $esi

; CHECK-LABEL: name: test_sdiv_i16
; CHECK: liveins: $edi, $esi
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: $ax = COPY [[SDIV]](s16)
; CHECK-NEXT: RET 0, implicit $ax
%2:_(s32) = COPY $edi
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $esi
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SDIV %0, %1
$ax = COPY %4(s16)
RET 0, implicit $ax

...
---
name: test_sdiv_i32
tracksRegLiveness: true
body: |
bb.1:
liveins: $edi, $esi

; CHECK-LABEL: name: test_sdiv_i32
; CHECK: liveins: $edi, $esi
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]]
; CHECK-NEXT: $eax = COPY [[SDIV]](s32)
; CHECK-NEXT: RET 0, implicit $eax
%0:_(s32) = COPY $edi
%1:_(s32) = COPY $esi
%2:_(s32) = G_SDIV %0, %1
$eax = COPY %2(s32)
RET 0, implicit $eax

...
---
name: test_sdiv_i64
tracksRegLiveness: true
body: |
bb.1:
; X64-LABEL: name: test_sdiv_i64
; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[DEF]], [[DEF1]]
; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[SDIV]](s64)
; X64-NEXT: RET 0, implicit [[COPY]](s64)
;
; X86-LABEL: name: test_sdiv_i64
; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: ADJCALLSTACKDOWN32 16, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
; X86-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $esp
; X86-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; X86-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; X86-NEXT: G_STORE [[UV]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 1)
; X86-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $esp
; X86-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; X86-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s32)
; X86-NEXT: G_STORE [[UV1]](s32), [[PTR_ADD1]](p0) :: (store (s32) into stack + 4, align 1)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; X86-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $esp
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; X86-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s32)
; X86-NEXT: G_STORE [[UV2]](s32), [[PTR_ADD2]](p0) :: (store (s32) into stack + 8, align 1)
; X86-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $esp
; X86-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; X86-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY3]], [[C3]](s32)
; X86-NEXT: G_STORE [[UV3]](s32), [[PTR_ADD3]](p0) :: (store (s32) into stack + 12, align 1)
; X86-NEXT: CALLpcrel32 &__divdi3, csr_32, implicit $esp, implicit $ssp, implicit-def $eax, implicit-def $edx
; X86-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $eax
; X86-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $edx
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
; X86-NEXT: ADJCALLSTACKUP32 16, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp
; X86-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; X86-NEXT: RET 0, implicit [[COPY6]](s64)
%0:_(s64) = IMPLICIT_DEF
%1:_(s64) = IMPLICIT_DEF
%2:_(s64) = G_SDIV %0, %1
%3:_(s64) = COPY %2(s64)
RET 0, implicit %3

...
127 changes: 127 additions & 0 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-srem.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,127 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,X64
# RUN: llc -mtriple=i686-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,X86

...
---
name: test_srem_i8
tracksRegLiveness: true
body: |
bb.1:
liveins: $edi, $esi

; CHECK-LABEL: name: test_srem_i8
; CHECK: liveins: $edi, $esi
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[SREM:%[0-9]+]]:_(s8) = G_SREM [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: $al = COPY [[SREM]](s8)
; CHECK-NEXT: RET 0, implicit $al
%2:_(s32) = COPY $edi
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $esi
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SREM %0, %1
$al = COPY %4(s8)
RET 0, implicit $al

...
---
name: test_srem_i16
tracksRegLiveness: true
body: |
bb.1:
liveins: $edi, $esi

; CHECK-LABEL: name: test_srem_i16
; CHECK: liveins: $edi, $esi
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[SREM:%[0-9]+]]:_(s16) = G_SREM [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: $ax = COPY [[SREM]](s16)
; CHECK-NEXT: RET 0, implicit $ax
%2:_(s32) = COPY $edi
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $esi
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SREM %0, %1
$ax = COPY %4(s16)
RET 0, implicit $ax

...
---
name: test_srem_i32
tracksRegLiveness: true
body: |
bb.1:
liveins: $edi, $esi

; CHECK-LABEL: name: test_srem_i32
; CHECK: liveins: $edi, $esi
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
; CHECK-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[COPY1]]
; CHECK-NEXT: $eax = COPY [[SREM]](s32)
; CHECK-NEXT: RET 0, implicit $eax
%0:_(s32) = COPY $edi
%1:_(s32) = COPY $esi
%2:_(s32) = G_SREM %0, %1
$eax = COPY %2(s32)
RET 0, implicit $eax

...
---
name: test_srem_i64
tracksRegLiveness: true
body: |
bb.1:
; X64-LABEL: name: test_srem_i64
; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[DEF]], [[DEF1]]
; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[SREM]](s64)
; X64-NEXT: RET 0, implicit [[COPY]](s64)
;
; X86-LABEL: name: test_srem_i64
; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: ADJCALLSTACKDOWN32 16, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
; X86-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $esp
; X86-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; X86-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; X86-NEXT: G_STORE [[UV]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 1)
; X86-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $esp
; X86-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; X86-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s32)
; X86-NEXT: G_STORE [[UV1]](s32), [[PTR_ADD1]](p0) :: (store (s32) into stack + 4, align 1)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; X86-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $esp
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; X86-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s32)
; X86-NEXT: G_STORE [[UV2]](s32), [[PTR_ADD2]](p0) :: (store (s32) into stack + 8, align 1)
; X86-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $esp
; X86-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; X86-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY3]], [[C3]](s32)
; X86-NEXT: G_STORE [[UV3]](s32), [[PTR_ADD3]](p0) :: (store (s32) into stack + 12, align 1)
; X86-NEXT: CALLpcrel32 &__moddi3, csr_32, implicit $esp, implicit $ssp, implicit-def $eax, implicit-def $edx
; X86-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $eax
; X86-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $edx
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
; X86-NEXT: ADJCALLSTACKUP32 16, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp
; X86-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; X86-NEXT: RET 0, implicit [[COPY6]](s64)
%0:_(s64) = IMPLICIT_DEF
%1:_(s64) = IMPLICIT_DEF
%2:_(s64) = G_SREM %0, %1
%3:_(s64) = COPY %2(s64)
RET 0, implicit %3

...
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