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[TargetLowering] Emit SIGN_EXTEND_INREG instead of shift pair from optimizeSetCCOfSignedTruncationCheck. #81785

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Merged
merged 4 commits into from
Feb 15, 2024
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[TargetLowering] Emit SIGN_EXTEND_INREG instead of shift pair from optimizeSetCCOfSignedTruncationCheck. #81785

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b1fbe46
[TargetLowering] Emit SIGN_EXTEND_INREG instead of shift pair from op…
topperc Feb 14, 2024
f0a6ffc
fixup! fix typo in comment
topperc Feb 15, 2024
7cfd98c
fixup! fix mistake in last commit
topperc Feb 15, 2024
f722dcc
fixup! remove extra paren from comment.
topperc Feb 15, 2024
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15 changes: 5 additions & 10 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4084,17 +4084,12 @@ SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck(
XVT, KeptBits))
return SDValue();

const unsigned MaskedBits = XVT.getSizeInBits() - KeptBits;
assert(MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable");

// Unfold into: ((%x << C) a>> C) cond %x
// Unfold into: sext_inreg(%x) cond %x
// Where 'cond' will be either 'eq' or 'ne'.
SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT);
SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt);
SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt);
SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, X, NewCond);

return T2;
SDValue SExtInReg = DAG.getNode(
ISD::SIGN_EXTEND_INREG, DL, XVT, X,
DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), KeptBits)));
return DAG.getSetCC(DL, SCCVT, SExtInReg, X, NewCond);
}

// (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0
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