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[LLVM] Adjust argument passing for APInt. NFC. #81814

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[LLVM] Adjust argument passing for APInt. NFC. #81814

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26 changes: 14 additions & 12 deletions llvm/include/llvm/Analysis/TargetTransformInfo.h
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Expand Up @@ -666,14 +666,15 @@ class TargetTransformInfo {
IntrinsicInst & II) const;
/// Can be used to implement target-specific instruction combining.
/// \see instCombineIntrinsic
std::optional<Value *> simplifyDemandedUseBitsIntrinsic(
InstCombiner & IC, IntrinsicInst & II, APInt DemandedMask,
KnownBits & Known, bool &KnownBitsComputed) const;
std::optional<Value *>
simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
const APInt &DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) const;
/// Can be used to implement target-specific instruction combining.
/// \see instCombineIntrinsic
std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner & IC, IntrinsicInst & II, APInt DemandedElts,
APInt & UndefElts, APInt & UndefElts2, APInt & UndefElts3,
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const;
/// @}
Expand Down Expand Up @@ -1839,11 +1840,12 @@ class TargetTransformInfo::Concept {
getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) = 0;
virtual std::optional<Instruction *> instCombineIntrinsic(
InstCombiner &IC, IntrinsicInst &II) = 0;
virtual std::optional<Value *> simplifyDemandedUseBitsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask,
KnownBits & Known, bool &KnownBitsComputed) = 0;
virtual std::optional<Value *>
simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
const APInt &DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) = 0;
virtual std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts,
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) = 0;
Expand Down Expand Up @@ -2293,14 +2295,14 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
}
std::optional<Value *>
simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
APInt DemandedMask, KnownBits &Known,
const APInt &DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) override {
return Impl.simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
KnownBitsComputed);
}
std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) override {
return Impl.simplifyDemandedVectorEltsIntrinsic(
Expand Down
6 changes: 3 additions & 3 deletions llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
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Expand Up @@ -194,14 +194,14 @@ class TargetTransformInfoImplBase {

std::optional<Value *>
simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
APInt DemandedMask, KnownBits &Known,
const APInt &DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) const {
return std::nullopt;
}

std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const {
return std::nullopt;
Expand Down
6 changes: 3 additions & 3 deletions llvm/include/llvm/CodeGen/BasicTTIImpl.h
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Expand Up @@ -682,15 +682,15 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {

std::optional<Value *>
simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
APInt DemandedMask, KnownBits &Known,
const APInt &DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) {
return BaseT::simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
KnownBitsComputed);
}

std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) {
return BaseT::simplifyDemandedVectorEltsIntrinsic(
Expand Down
9 changes: 4 additions & 5 deletions llvm/include/llvm/Transforms/InstCombine/InstCombiner.h
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Expand Up @@ -348,12 +348,11 @@ class LLVM_LIBRARY_VISIBILITY InstCombiner {

// Call target specific combiners
std::optional<Instruction *> targetInstCombineIntrinsic(IntrinsicInst &II);
std::optional<Value *>
targetSimplifyDemandedUseBitsIntrinsic(IntrinsicInst &II, APInt DemandedMask,
KnownBits &Known,
bool &KnownBitsComputed);
std::optional<Value *> targetSimplifyDemandedUseBitsIntrinsic(
IntrinsicInst &II, const APInt &DemandedMask, KnownBits &Known,
bool &KnownBitsComputed);
std::optional<Value *> targetSimplifyDemandedVectorEltsIntrinsic(
IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
IntrinsicInst &II, const APInt &DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp);
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Analysis/TargetTransformInfo.cpp
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Expand Up @@ -365,15 +365,15 @@ TargetTransformInfo::instCombineIntrinsic(InstCombiner &IC,
}

std::optional<Value *> TargetTransformInfo::simplifyDemandedUseBitsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) const {
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedMask,
KnownBits &Known, bool &KnownBitsComputed) const {
return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
KnownBitsComputed);
}

std::optional<Value *> TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const {
return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
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Expand Up @@ -2107,7 +2107,7 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
}

std::optional<Value *> AArch64TTIImpl::simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt OrigDemandedElts,
InstCombiner &IC, IntrinsicInst &II, const APInt &OrigDemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const {
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
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Expand Up @@ -125,8 +125,8 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
IntrinsicInst &II) const;

std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const;

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
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Expand Up @@ -1370,8 +1370,8 @@ static Value *simplifyAMDGCNMemoryIntrinsicDemanded(InstCombiner &IC,
}

std::optional<Value *> GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const {
switch (II.getIntrinsicID()) {
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
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Expand Up @@ -223,8 +223,8 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const;
std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const;

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
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Expand Up @@ -253,7 +253,7 @@ ARMTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
}

std::optional<Value *> ARMTTIImpl::simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt OrigDemandedElts,
InstCombiner &IC, IntrinsicInst &II, const APInt &OrigDemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const {
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMTargetTransformInfo.h
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Expand Up @@ -122,8 +122,8 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const;
std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const;

Expand Down
34 changes: 17 additions & 17 deletions llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
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Expand Up @@ -2813,8 +2813,8 @@ X86TTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
}

std::optional<Value *> X86TTIImpl::simplifyDemandedUseBitsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) const {
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedMask,
KnownBits &Known, bool &KnownBitsComputed) const {
switch (II.getIntrinsicID()) {
default:
break;
Expand Down Expand Up @@ -2853,16 +2853,16 @@ std::optional<Value *> X86TTIImpl::simplifyDemandedUseBitsIntrinsic(
}

std::optional<Value *> X86TTIImpl::simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
simplifyAndSetOp) const {
unsigned VWidth = cast<FixedVectorType>(II.getType())->getNumElements();
switch (II.getIntrinsicID()) {
default:
break;
case Intrinsic::x86_xop_vfrcz_ss:
case Intrinsic::x86_xop_vfrcz_sd:
case Intrinsic::x86_xop_vfrcz_sd: {
// The instructions for these intrinsics are speced to zero upper bits not
// pass them through like other scalar intrinsics. So we shouldn't just
// use Arg0 if DemandedElts[0] is clear like we do for other intrinsics.
Expand All @@ -2873,13 +2873,13 @@ std::optional<Value *> X86TTIImpl::simplifyDemandedVectorEltsIntrinsic(
}

// Only the lower element is used.
DemandedElts = 1;
simplifyAndSetOp(&II, 0, DemandedElts, UndefElts);
APInt OpDemandedElts(DemandedElts.getBitWidth(), 1);
simplifyAndSetOp(&II, 0, OpDemandedElts, UndefElts);

// Only the lower element is undefined. The high elements are zero.
UndefElts = UndefElts[0];
break;

}
// Unary scalar-as-vector operations that work column-wise.
case Intrinsic::x86_sse_rcp_ss:
case Intrinsic::x86_sse_rsqrt_ss:
Expand Down Expand Up @@ -2912,8 +2912,8 @@ std::optional<Value *> X86TTIImpl::simplifyDemandedVectorEltsIntrinsic(
}

// Only lower element is used for operand 1.
DemandedElts = 1;
simplifyAndSetOp(&II, 1, DemandedElts, UndefElts2);
APInt OpDemandedElts(DemandedElts.getBitWidth(), 1);
simplifyAndSetOp(&II, 1, OpDemandedElts, UndefElts2);

// Lower element is undefined if both lower elements are undefined.
// Consider things like undef&0. The result is known zero, not undef.
Expand All @@ -2939,8 +2939,8 @@ std::optional<Value *> X86TTIImpl::simplifyDemandedVectorEltsIntrinsic(
}

// Only lower element is used for operand 1.
DemandedElts = 1;
simplifyAndSetOp(&II, 1, DemandedElts, UndefElts2);
APInt OpDemandedElts(DemandedElts.getBitWidth(), 1);
simplifyAndSetOp(&II, 1, OpDemandedElts, UndefElts2);

// Take the high undef elements from operand 0 and take the lower element
// from operand 1.
Expand All @@ -2963,7 +2963,7 @@ std::optional<Value *> X86TTIImpl::simplifyDemandedVectorEltsIntrinsic(
case Intrinsic::x86_avx512_mask_mul_sd_round:
case Intrinsic::x86_avx512_mask_sub_sd_round:
case Intrinsic::x86_avx512_mask_max_sd_round:
case Intrinsic::x86_avx512_mask_min_sd_round:
case Intrinsic::x86_avx512_mask_min_sd_round: {
simplifyAndSetOp(&II, 0, DemandedElts, UndefElts);

// If lowest element of a scalar op isn't used then use Arg0.
Expand All @@ -2973,16 +2973,16 @@ std::optional<Value *> X86TTIImpl::simplifyDemandedVectorEltsIntrinsic(
}

// Only lower element is used for operand 1 and 2.
DemandedElts = 1;
simplifyAndSetOp(&II, 1, DemandedElts, UndefElts2);
simplifyAndSetOp(&II, 2, DemandedElts, UndefElts3);
APInt OpDemandedElts(DemandedElts.getBitWidth(), 1);
simplifyAndSetOp(&II, 1, OpDemandedElts, UndefElts2);
simplifyAndSetOp(&II, 2, OpDemandedElts, UndefElts3);

// Lower element is undefined if all three lower elements are undefined.
// Consider things like undef&0. The result is known zero, not undef.
if (!UndefElts2[0] || !UndefElts3[0])
UndefElts.clearBit(0);
break;

}
// TODO: Add fmaddsub support?
case Intrinsic::x86_sse3_addsub_pd:
case Intrinsic::x86_sse3_addsub_ps:
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/X86/X86TargetTransformInfo.h
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Expand Up @@ -196,11 +196,11 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
IntrinsicInst &II) const;
std::optional<Value *>
simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
APInt DemandedMask, KnownBits &Known,
const APInt &DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) const;
std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
InstCombiner &IC, IntrinsicInst &II, const APInt &DemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const;

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
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Expand Up @@ -162,7 +162,7 @@ InstCombiner::targetInstCombineIntrinsic(IntrinsicInst &II) {
}

std::optional<Value *> InstCombiner::targetSimplifyDemandedUseBitsIntrinsic(
IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
IntrinsicInst &II, const APInt &DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) {
// Handle target specific intrinsics
if (II.getCalledFunction()->isTargetIntrinsic()) {
Expand All @@ -173,7 +173,7 @@ std::optional<Value *> InstCombiner::targetSimplifyDemandedUseBitsIntrinsic(
}

std::optional<Value *> InstCombiner::targetSimplifyDemandedVectorEltsIntrinsic(
IntrinsicInst &II, APInt DemandedElts, APInt &PoisonElts,
IntrinsicInst &II, const APInt &DemandedElts, APInt &PoisonElts,
APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) {
Expand Down