Skip to content

[AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN,SMAX,UMIN,UMAX} for odd-sized vectors #81831

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
wants to merge 1 commit into from
Closed

[AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN,SMAX,UMIN,UMAX} for odd-sized vectors #81831

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 7 additions & 0 deletions llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1070,6 +1070,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{s16, v8s16},
{s32, v2s32},
{s32, v4s32}})
.moreElementsIf(
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think this can happen for more than just odd numbers, if we have support in the legalizer. I think I would make it moreElementsToNextPow2 unless there is a big reason not to.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

As I noted in my commit message, unfortunately that causes regressions for odd-sized i8 vectors: https://gist.github.com/dc03-work/3d749a7be0dc893d86d2df0fbc31709a (except for the very last case... for some reason). I was noticing another test failure when I enabled it for even-sized vectors, however that seems to have gone away now.

[=](const LegalityQuery &Query) {
return Query.Types[1].isVector() &&
Query.Types[1].getElementType() != s8 &&
Query.Types[1].getNumElements() & 1;
},
LegalizeMutations::moreElementsToNextPow2(1))
.clampMaxNumElements(1, s64, 2)
.clampMaxNumElements(1, s32, 4)
.clampMaxNumElements(1, s16, 8)
Expand Down
191 changes: 47 additions & 144 deletions llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -595,30 +595,14 @@ entry:
}

define i16 @sminv_v3i16(<3 x i16> %a) {
; CHECK-SD-LABEL: sminv_v3i16:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: mov w8, #32767 // =0x7fff
; CHECK-SD-NEXT: mov v0.h[3], w8
; CHECK-SD-NEXT: sminv h0, v0.4h
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sminv_v3i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: mov h1, v0.h[1]
; CHECK-GI-NEXT: smov w8, v0.h[0]
; CHECK-GI-NEXT: umov w9, v0.h[0]
; CHECK-GI-NEXT: umov w10, v0.h[1]
; CHECK-GI-NEXT: smov w11, v0.h[2]
; CHECK-GI-NEXT: umov w13, v0.h[2]
; CHECK-GI-NEXT: fmov w12, s1
; CHECK-GI-NEXT: cmp w8, w12, sxth
; CHECK-GI-NEXT: csel w8, w9, w10, lt
; CHECK-GI-NEXT: cmp w11, w8, sxth
; CHECK-GI-NEXT: csel w0, w8, w13, gt
; CHECK-GI-NEXT: ret
; CHECK-LABEL: sminv_v3i16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, #32767 // =0x7fff
; CHECK-NEXT: mov v0.h[3], w8
; CHECK-NEXT: sminv h0, v0.4h
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
%arg1 = call i16 @llvm.vector.reduce.smin.v3i16(<3 x i16> %a)
ret i16 %arg1
Expand Down Expand Up @@ -670,28 +654,13 @@ entry:
}

define i32 @sminv_v3i32(<3 x i32> %a) {
; CHECK-SD-LABEL: sminv_v3i32:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov w8, #2147483647 // =0x7fffffff
; CHECK-SD-NEXT: mov v0.s[3], w8
; CHECK-SD-NEXT: sminv s0, v0.4s
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sminv_v3i32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: mov s2, v0.s[2]
; CHECK-GI-NEXT: fmov w9, s1
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: fmov w9, s2
; CHECK-GI-NEXT: fcsel s0, s0, s1, lt
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: fcsel s0, s0, s2, lt
; CHECK-GI-NEXT: fmov w0, s0
; CHECK-GI-NEXT: ret
; CHECK-LABEL: sminv_v3i32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #2147483647 // =0x7fffffff
; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: sminv s0, v0.4s
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
%arg1 = call i32 @llvm.vector.reduce.smin.v3i32(<3 x i32> %a)
ret i32 %arg1
Expand Down Expand Up @@ -972,17 +941,10 @@ define i16 @smaxv_v3i16(<3 x i16> %a) {
; CHECK-GI-LABEL: smaxv_v3i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: mov h1, v0.h[1]
; CHECK-GI-NEXT: smov w8, v0.h[0]
; CHECK-GI-NEXT: umov w9, v0.h[0]
; CHECK-GI-NEXT: umov w10, v0.h[1]
; CHECK-GI-NEXT: smov w11, v0.h[2]
; CHECK-GI-NEXT: umov w13, v0.h[2]
; CHECK-GI-NEXT: fmov w12, s1
; CHECK-GI-NEXT: cmp w8, w12, sxth
; CHECK-GI-NEXT: csel w8, w9, w10, gt
; CHECK-GI-NEXT: cmp w11, w8, sxth
; CHECK-GI-NEXT: csel w0, w8, w13, lt
; CHECK-GI-NEXT: mov w8, #32768 // =0x8000
; CHECK-GI-NEXT: mov v0.h[3], w8
; CHECK-GI-NEXT: smaxv h0, v0.4h
; CHECK-GI-NEXT: fmov w0, s0
; CHECK-GI-NEXT: ret
entry:
%arg1 = call i16 @llvm.vector.reduce.smax.v3i16(<3 x i16> %a)
Expand Down Expand Up @@ -1035,28 +997,13 @@ entry:
}

define i32 @smaxv_v3i32(<3 x i32> %a) {
; CHECK-SD-LABEL: smaxv_v3i32:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov w8, #-2147483648 // =0x80000000
; CHECK-SD-NEXT: mov v0.s[3], w8
; CHECK-SD-NEXT: smaxv s0, v0.4s
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: smaxv_v3i32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: mov s2, v0.s[2]
; CHECK-GI-NEXT: fmov w9, s1
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: fmov w9, s2
; CHECK-GI-NEXT: fcsel s0, s0, s1, gt
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: fcsel s0, s0, s2, gt
; CHECK-GI-NEXT: fmov w0, s0
; CHECK-GI-NEXT: ret
; CHECK-LABEL: smaxv_v3i32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000
; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: smaxv s0, v0.4s
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
%arg1 = call i32 @llvm.vector.reduce.smax.v3i32(<3 x i32> %a)
ret i32 %arg1
Expand Down Expand Up @@ -1335,17 +1282,10 @@ define i16 @uminv_v3i16(<3 x i16> %a) {
; CHECK-GI-LABEL: uminv_v3i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: mov h1, v0.h[1]
; CHECK-GI-NEXT: umov w8, v0.h[0]
; CHECK-GI-NEXT: umov w9, v0.h[0]
; CHECK-GI-NEXT: umov w10, v0.h[1]
; CHECK-GI-NEXT: umov w11, v0.h[2]
; CHECK-GI-NEXT: umov w13, v0.h[2]
; CHECK-GI-NEXT: fmov w12, s1
; CHECK-GI-NEXT: cmp w8, w12, uxth
; CHECK-GI-NEXT: csel w8, w9, w10, lo
; CHECK-GI-NEXT: cmp w11, w8, uxth
; CHECK-GI-NEXT: csel w0, w8, w13, hi
; CHECK-GI-NEXT: mov w8, #65535 // =0xffff
; CHECK-GI-NEXT: mov v0.h[3], w8
; CHECK-GI-NEXT: uminv h0, v0.4h
; CHECK-GI-NEXT: fmov w0, s0
; CHECK-GI-NEXT: ret
entry:
%arg1 = call i16 @llvm.vector.reduce.umin.v3i16(<3 x i16> %a)
Expand Down Expand Up @@ -1398,28 +1338,13 @@ entry:
}

define i32 @uminv_v3i32(<3 x i32> %a) {
; CHECK-SD-LABEL: uminv_v3i32:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov w8, #-1 // =0xffffffff
; CHECK-SD-NEXT: mov v0.s[3], w8
; CHECK-SD-NEXT: uminv s0, v0.4s
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: uminv_v3i32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: mov s2, v0.s[2]
; CHECK-GI-NEXT: fmov w9, s1
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: fmov w9, s2
; CHECK-GI-NEXT: fcsel s0, s0, s1, lo
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: fcsel s0, s0, s2, lo
; CHECK-GI-NEXT: fmov w0, s0
; CHECK-GI-NEXT: ret
; CHECK-LABEL: uminv_v3i32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #-1 // =0xffffffff
; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: uminv s0, v0.4s
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
%arg1 = call i32 @llvm.vector.reduce.umin.v3i32(<3 x i32> %a)
ret i32 %arg1
Expand Down Expand Up @@ -1697,17 +1622,10 @@ define i16 @umaxv_v3i16(<3 x i16> %a) {
; CHECK-GI-LABEL: umaxv_v3i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: mov h1, v0.h[1]
; CHECK-GI-NEXT: umov w8, v0.h[0]
; CHECK-GI-NEXT: umov w9, v0.h[0]
; CHECK-GI-NEXT: umov w10, v0.h[1]
; CHECK-GI-NEXT: umov w11, v0.h[2]
; CHECK-GI-NEXT: umov w13, v0.h[2]
; CHECK-GI-NEXT: fmov w12, s1
; CHECK-GI-NEXT: cmp w8, w12, uxth
; CHECK-GI-NEXT: csel w8, w9, w10, hi
; CHECK-GI-NEXT: cmp w11, w8, uxth
; CHECK-GI-NEXT: csel w0, w8, w13, lo
; CHECK-GI-NEXT: mov w8, #0 // =0x0
; CHECK-GI-NEXT: mov v0.h[3], w8
; CHECK-GI-NEXT: umaxv h0, v0.4h
; CHECK-GI-NEXT: fmov w0, s0
; CHECK-GI-NEXT: ret
entry:
%arg1 = call i16 @llvm.vector.reduce.umax.v3i16(<3 x i16> %a)
Expand Down Expand Up @@ -1760,27 +1678,12 @@ entry:
}

define i32 @umaxv_v3i32(<3 x i32> %a) {
; CHECK-SD-LABEL: umaxv_v3i32:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov v0.s[3], wzr
; CHECK-SD-NEXT: umaxv s0, v0.4s
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: umaxv_v3i32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: mov s2, v0.s[2]
; CHECK-GI-NEXT: fmov w9, s1
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: fmov w9, s2
; CHECK-GI-NEXT: fcsel s0, s0, s1, hi
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: fcsel s0, s0, s2, hi
; CHECK-GI-NEXT: fmov w0, s0
; CHECK-GI-NEXT: ret
; CHECK-LABEL: umaxv_v3i32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.s[3], wzr
; CHECK-NEXT: umaxv s0, v0.4s
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
%arg1 = call i32 @llvm.vector.reduce.umax.v3i32(<3 x i32> %a)
ret i32 %arg1
Expand Down
27 changes: 6 additions & 21 deletions llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -200,27 +200,12 @@ define i8 @test_v9i8(<9 x i8> %a) nounwind {
}

define i32 @test_v3i32(<3 x i32> %a) nounwind {
; CHECK-SD-LABEL: test_v3i32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov v0.s[3], wzr
; CHECK-SD-NEXT: umaxv s0, v0.4s
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_v3i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: mov s2, v0.s[2]
; CHECK-GI-NEXT: fmov w9, s1
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: fmov w9, s2
; CHECK-GI-NEXT: fcsel s0, s0, s1, hi
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: fcsel s0, s0, s2, hi
; CHECK-GI-NEXT: fmov w0, s0
; CHECK-GI-NEXT: ret
; CHECK-LABEL: test_v3i32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov v0.s[3], wzr
; CHECK-NEXT: umaxv s0, v0.4s
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
%b = call i32 @llvm.vector.reduce.umax.v3i32(<3 x i32> %a)
ret i32 %b
}
Expand Down
You are viewing a condensed version of this merge commit. You can view the full changes here.