[AArch64] Intrinsics aarch64_{get,set}_fpsr

llvm/include/llvm/IR/IntrinsicsAArch64.td

@@ -703,17 +703,19 @@ def int_aarch64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic;
 def int_aarch64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic;
 
 let TargetPrefix = "aarch64" in {
-  class FPCR_Get_Intrinsic
+  class FPENV_Get_Intrinsic
     : DefaultAttrsIntrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrHasSideEffects]>;
-  class FPCR_Set_Intrinsic
+  class FPENV_Set_Intrinsic
     : DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrNoMem, IntrHasSideEffects]>;
   class RNDR_Intrinsic
     : DefaultAttrsIntrinsic<[llvm_i64_ty, llvm_i1_ty], [], [IntrNoMem, IntrHasSideEffects]>;
 }
 
-// FPCR
-def int_aarch64_get_fpcr : FPCR_Get_Intrinsic;
-def int_aarch64_set_fpcr : FPCR_Set_Intrinsic;
+// FP environment registers.
+def int_aarch64_get_fpcr : FPENV_Get_Intrinsic;
+def int_aarch64_set_fpcr : FPENV_Set_Intrinsic;
+def int_aarch64_get_fpsr : FPENV_Get_Intrinsic;
+def int_aarch64_set_fpsr : FPENV_Set_Intrinsic;
 
 // Armv8.5-A Random number generation intrinsics
 def int_aarch64_rndr : RNDR_Intrinsic;

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -1805,7 +1805,7 @@ def HWASAN_CHECK_MEMACCESS_SHORTGRANULES : Pseudo<
 // The virtual cycle counter register is CNTVCT_EL0.
 def : Pat<(readcyclecounter), (MRS 0xdf02)>;
 
-// FPCR register
+// FPCR and FPSR registers.
 let Uses = [FPCR] in
 def MRS_FPCR : Pseudo<(outs GPR64:$dst), (ins),
                       [(set GPR64:$dst, (int_aarch64_get_fpcr))]>,
@@ -1817,6 +1817,17 @@ def MSR_FPCR : Pseudo<(outs), (ins GPR64:$val),
                PseudoInstExpansion<(MSR 0xda20, GPR64:$val)>,
                Sched<[WriteSys]>;
 
+let Uses = [FPSR] in
+def MRS_FPSR : Pseudo<(outs GPR64:$dst), (ins),
+                      [(set GPR64:$dst, (int_aarch64_get_fpsr))]>,
+               PseudoInstExpansion<(MRS GPR64:$dst, 0xda21)>,
+               Sched<[WriteSys]>;
+let Defs = [FPSR] in
+def MSR_FPSR : Pseudo<(outs), (ins GPR64:$val),
+                      [(int_aarch64_set_fpsr i64:$val)]>,
+               PseudoInstExpansion<(MSR 0xda21, GPR64:$val)>,
+               Sched<[WriteSys]>;
+
 // Generic system instructions
 def SYSxt  : SystemXtI<0, "sys">;
 def SYSLxt : SystemLXtI<1, "sysl">;

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

@@ -147,6 +147,9 @@ def VG : AArch64Reg<0, "vg">, DwarfRegNum<[46]>;
 // Floating-point control register
 def FPCR : AArch64Reg<0, "fpcr">;
 
+// Floating-point status register.
+def FPSR : AArch64Reg<0, "fpsr">;
+
 // GPR register classes with the intersections of GPR32/GPR32sp and
 // GPR64/GPR64sp for use by the coalescer.
 def GPR32common : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 30)> {

llvm/test/CodeGen/AArch64/arm64-fpenv.ll

@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
+
+define i64 @get_fpcr() #0 {
+; CHECK-LABEL: get_fpcr:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mrs x0, FPCR
+; CHECK-NEXT:    ret
+  %1 = tail call i64 @llvm.aarch64.get.fpcr()
+  ret i64 %1
+}
+
+define void @set_fpcr(i64 %cr) {
+; CHECK-LABEL: set_fpcr:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    msr FPCR, x0
+; CHECK-NEXT:    ret
+  call void @llvm.aarch64.set.fpcr(i64 %cr)
+  ret void
+}
+
+define i64 @get_fpsr() {
+; CHECK-LABEL: get_fpsr:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mrs x0, FPSR
+; CHECK-NEXT:    ret
+  %1 = tail call i64 @llvm.aarch64.get.fpsr()
+  ret i64 %1
+}
+
+define void @set_fpsr(i64 %sr) {
+; CHECK-LABEL: set_fpsr:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    msr FPSR, x0
+; CHECK-NEXT:    ret
+  call void @llvm.aarch64.set.fpsr(i64 %sr)
+  ret void
+}
+
+declare i64 @llvm.aarch64.get.fpcr()
+declare void @llvm.aarch64.set.fpcr(i64)
+declare i64 @llvm.aarch64.get.fpsr()
+declare void @llvm.aarch64.set.fpsr(i64)
+
+attributes #0 = { nounwind }