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Initialize unsigned integer when declared #81894

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Merged
merged 2 commits into from
Feb 25, 2024
Merged

Initialize unsigned integer when declared #81894

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88d095f
Initialize unsigned integer when declared
Feb 15, 2024
e9c92ef
Extend unsigned integer initialization
Feb 19, 2024
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9 changes: 5 additions & 4 deletions llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3261,15 +3261,16 @@ bool AMDGPUDAGToDAGISel::SelectWMMAModsF32NegAbs(SDValue In, SDValue &Src,
SDValue &SrcMods) const {
Src = In;
unsigned Mods = SISrcMods::OP_SEL_1;
unsigned ModOpcode;
SmallVector<SDValue, 8> EltsF32;

if (auto *BV = dyn_cast<BuildVectorSDNode>(stripBitcast(In))) {
assert(BV->getNumOperands() > 0);
// Based on first element decide which mod we match, neg or abs
SDValue ElF32 = stripBitcast(BV->getOperand(0));
unsigned ModOpcode =
(ElF32.getOpcode() == ISD::FNEG) ? ISD::FNEG : ISD::FABS;
for (unsigned i = 0; i < BV->getNumOperands(); ++i) {
SDValue ElF32 = stripBitcast(BV->getOperand(i));
// Based on first element decide which mod we match, neg or abs
if (EltsF32.empty())
ModOpcode = (ElF32.getOpcode() == ISD::FNEG) ? ISD::FNEG : ISD::FABS;
if (ElF32.getOpcode() != ModOpcode)
break;
EltsF32.push_back(ElF32.getOperand(0));
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27 changes: 15 additions & 12 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4019,16 +4019,17 @@ InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectWMMAModsF32NegAbs(MachineOperand &Root) const {
Register Src = Root.getReg();
unsigned Mods = SISrcMods::OP_SEL_1;
unsigned ModOpcode;
SmallVector<Register, 8> EltsF32;

if (GBuildVector *BV = dyn_cast<GBuildVector>(MRI->getVRegDef(Src))) {
assert(BV->getNumSources() > 0);
// Based on first element decide which mod we match, neg or abs
MachineInstr *ElF32 = MRI->getVRegDef(BV->getSourceReg(0));
unsigned ModOpcode = (ElF32->getOpcode() == AMDGPU::G_FNEG)
? AMDGPU::G_FNEG
: AMDGPU::G_FABS;
for (unsigned i = 0; i < BV->getNumSources(); ++i) {
MachineInstr *ElF32 = MRI->getVRegDef(BV->getSourceReg(i));
// Based on first element decide which mod we match, neg or abs
if (EltsF32.empty())
ModOpcode = (ElF32->getOpcode() == AMDGPU::G_FNEG) ? AMDGPU::G_FNEG
: AMDGPU::G_FABS;
ElF32 = MRI->getVRegDef(BV->getSourceReg(i));
if (ElF32->getOpcode() != ModOpcode)
break;
EltsF32.push_back(ElF32->getOperand(1).getReg());
Expand Down Expand Up @@ -4075,16 +4076,18 @@ InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectWMMAModsF16NegAbs(MachineOperand &Root) const {
Register Src = Root.getReg();
unsigned Mods = SISrcMods::OP_SEL_1;
unsigned ModOpcode;
SmallVector<Register, 8> EltsV2F16;

if (GConcatVectors *CV = dyn_cast<GConcatVectors>(MRI->getVRegDef(Src))) {
assert(CV->getNumSources() > 0);
MachineInstr *ElV2F16 = MRI->getVRegDef(CV->getSourceReg(0));
// Based on first element decide which mod we match, neg or abs
unsigned ModOpcode = (ElV2F16->getOpcode() == AMDGPU::G_FNEG)
? AMDGPU::G_FNEG
: AMDGPU::G_FABS;

for (unsigned i = 0; i < CV->getNumSources(); ++i) {
MachineInstr *ElV2F16 = MRI->getVRegDef(CV->getSourceReg(i));
// Based on first element decide which mod we match, neg or abs
if (EltsV2F16.empty())
ModOpcode = (ElV2F16->getOpcode() == AMDGPU::G_FNEG) ? AMDGPU::G_FNEG
: AMDGPU::G_FABS;
ElV2F16 = MRI->getVRegDef(CV->getSourceReg(i));
if (ElV2F16->getOpcode() != ModOpcode)
break;
EltsV2F16.push_back(ElV2F16->getOperand(1).getReg());
Expand Down