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[AMDGPU] Consolidate SGPRSpill and VGPRSpill into single Spill bit #81901

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Merged
merged 6 commits into from
Feb 16, 2024
Merged

[AMDGPU] Consolidate SGPRSpill and VGPRSpill into single Spill bit #81901

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b438f06
[AMDGPU] Consolidate SGPRSpill and VGPRSpill into single Spill bit to…
CRobeck Feb 14, 2024
df46f5f
fix comment typo
CRobeck Feb 15, 2024
bf89a98
add some helper functions
CRobeck Feb 16, 2024
742c808
formatting
CRobeck Feb 16, 2024
fc25a1f
replace bitwise operators for boolean comparisons
CRobeck Feb 16, 2024
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fix comment
CRobeck Feb 16, 2024
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6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/SIDefines.h
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Original file line number Diff line number Diff line change
Expand Up @@ -87,9 +87,9 @@ enum : uint64_t {
FLAT = 1 << 24,
DS = 1 << 25,

// Pseudo instruction formats.
VGPRSpill = 1 << 26,
SGPRSpill = 1 << 27,
// Combined SGPR/VGPR Spill bit
// Logic to separate them out is done in isSGPRSpill and isVGPRSpill
Spill = 1 << 26,

// LDSDIR instruction format.
LDSDIR = 1 << 28,
Expand Down
11 changes: 6 additions & 5 deletions llvm/lib/Target/AMDGPU/SIInstrFormats.td
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Expand Up @@ -46,9 +46,8 @@ class InstSI <dag outs, dag ins, string asm = "",
field bit FLAT = 0;
field bit DS = 0;

// Pseudo instruction formats.
field bit VGPRSpill = 0;
field bit SGPRSpill = 0;
// Combined SGPR/VGPR spill bit
field bit Spill = 0;

// LDSDIR instruction format.
field bit LDSDIR = 0;
Expand Down Expand Up @@ -187,8 +186,10 @@ class InstSI <dag outs, dag ins, string asm = "",
let TSFlags{24} = FLAT;
let TSFlags{25} = DS;

let TSFlags{26} = VGPRSpill;
let TSFlags{27} = SGPRSpill;
let TSFlags{26} = Spill;

// Reserved, must be 0
let TSFlags{27} = 0;

let TSFlags{28} = LDSDIR;
let TSFlags{29} = VINTERP;
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -5424,7 +5424,7 @@ adjustAllocatableRegClass(const GCNSubtarget &ST, const SIRegisterInfo &RI,
bool IsAllocatable) {
if ((IsAllocatable || !ST.hasGFX90AInsts() || !MRI.reservedRegsFrozen()) &&
(((TID.mayLoad() || TID.mayStore()) &&
!(TID.TSFlags & SIInstrFlags::VGPRSpill)) ||
!(TID.TSFlags & SIInstrFlags::Spill)) ||
(TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::MIMG)))) {
switch (RCID) {
case AMDGPU::AV_32RegClassID:
Expand Down Expand Up @@ -8809,12 +8809,12 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,
IsNullOrVectorRegister = !RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg));
}

uint16_t Opc = MI.getOpcode();
uint16_t Opcode = MI.getOpcode();
// FIXME: Copies inserted in the block prolog for live-range split should also
// be included.
return IsNullOrVectorRegister &&
(isSpillOpcode(Opc) || (!MI.isTerminator() && Opc != AMDGPU::COPY &&
MI.modifiesRegister(AMDGPU::EXEC, &RI)));
(isSpill(Opcode) || (!MI.isTerminator() && Opcode != AMDGPU::COPY &&
MI.modifiesRegister(AMDGPU::EXEC, &RI)));
}

MachineInstrBuilder
Expand Down
30 changes: 23 additions & 7 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Expand Up @@ -708,25 +708,41 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
}

// SI_SPILL_S32_TO_VGPR and SI_RESTORE_S32_FROM_VGPR form a special case of
// SGPRs spilling to VGPRs which are SGPR spills but from VALU instructions
// therefore we need an explicit check for them since just checking if the
// Spill bit is set and what instruction type it came from misclassifies
// them.
static bool isVGPRSpill(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
return MI.getOpcode() != AMDGPU::SI_SPILL_S32_TO_VGPR &&
MI.getOpcode() != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
(isSpill(MI) && isVALU(MI));
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}

bool isVGPRSpill(uint16_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR &&
Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
(isSpill(Opcode) && isVALU(Opcode));
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}

static bool isSGPRSpill(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
return MI.getOpcode() == AMDGPU::SI_SPILL_S32_TO_VGPR ||
MI.getOpcode() == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
(isSpill(MI) && isSALU(MI));
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}

bool isSGPRSpill(uint16_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
return Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR ||
Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
(isSpill(Opcode) && isSALU(Opcode));
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}

bool isSpillOpcode(uint16_t Opcode) const {
return get(Opcode).TSFlags &
(SIInstrFlags::SGPRSpill | SIInstrFlags::VGPRSpill);
bool isSpill(uint16_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::Spill;
}

static bool isSpill(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::Spill;
}

static bool isWWMRegSpillOpcode(uint16_t Opcode) {
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/AMDGPU/SIInstructions.td
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Expand Up @@ -895,7 +895,7 @@ def V_INDIRECT_REG_READ_GPR_IDX_B32_V16 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VRe
def V_INDIRECT_REG_READ_GPR_IDX_B32_V32 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VReg_1024>;

multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
let UseNamedOperandTable = 1, SGPRSpill = 1, Uses = [EXEC] in {
let UseNamedOperandTable = 1, Spill = 1, SALU = 1, Uses = [EXEC] in {
def _SAVE : PseudoInstSI <
(outs),
(ins sgpr_class:$data, i32imm:$addr)> {
Expand Down Expand Up @@ -931,7 +931,7 @@ defm SI_SPILL_S384 : SI_SPILL_SGPR <SReg_384>;
defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
defm SI_SPILL_S1024 : SI_SPILL_SGPR <SReg_1024>;

let SGPRSpill = 1, VALU = 1, isConvergent = 1 in {
let Spill = 1, VALU = 1, isConvergent = 1 in {
def SI_SPILL_S32_TO_VGPR : PseudoInstSI <(outs VGPR_32:$vdst),
(ins SReg_32:$src0, i32imm:$src1, VGPR_32:$vdst_in)> {
let Size = 4;
Expand All @@ -951,13 +951,13 @@ def SI_RESTORE_S32_FROM_VGPR : PseudoInstSI <(outs SReg_32:$sdst),
let mayLoad = 0;
let mayStore = 0;
}
} // End SGPRSpill = 1, VALU = 1, isConvergent = 1
} // End Spill = 1, VALU = 1, isConvergent = 1

// VGPR or AGPR spill instructions. In case of AGPR spilling a temp register
// needs to be used and an extra instruction to move between VGPR and AGPR.
// UsesTmp adds to the total size of an expanded spill in this case.
multiclass SI_SPILL_VGPR <RegisterClass vgpr_class, bit UsesTmp = 0> {
let UseNamedOperandTable = 1, VGPRSpill = 1,
let UseNamedOperandTable = 1, Spill = 1, VALU = 1,
SchedRW = [WriteVMEM] in {
def _SAVE : VPseudoInstSI <
(outs),
Expand All @@ -983,7 +983,7 @@ multiclass SI_SPILL_VGPR <RegisterClass vgpr_class, bit UsesTmp = 0> {
// Size field is unsigned char and cannot fit more.
let Size = !if(!le(MaxSize, 256), MaxSize, 252);
}
} // End UseNamedOperandTable = 1, VGPRSpill = 1, SchedRW = [WriteVMEM]
} // End UseNamedOperandTable = 1, Spill = 1, VALU = 1, SchedRW = [WriteVMEM]
}

defm SI_SPILL_V32 : SI_SPILL_VGPR <VGPR_32>;
Expand Down