[Sparc] Use generated MatchRegisterName (NFCI)

[s-barannikov]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-sparc

Author: Sergei Barannikov (s-barannikov)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/82165.diff

2 Files Affected:

• (modified) llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (+114-311)
• (modified) llvm/lib/Target/Sparc/Sparc.td (+2-1)

diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 7a956636831df7..ee980296adabe1 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -57,6 +57,7 @@ class SparcOperand;
 
 class SparcAsmParser : public MCTargetAsmParser {
   MCAsmParser &Parser;
+  const MCRegisterInfo &MRI;
 
   enum class TailRelocKind { Load_GOT, Add_TLS, Load_TLS, Call_TLS };
 
@@ -109,7 +110,7 @@ class SparcAsmParser : public MCTargetAsmParser {
                                          const MCExpr *subExpr);
 
   // returns true if Tok is matched to a register and returns register in RegNo.
-  bool matchRegisterName(const AsmToken &Tok, MCRegister &RegNo,
+  bool matchRegisterName(const AsmToken &Tok, MCRegister &Reg,
                          unsigned &RegKind);
 
   bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
@@ -128,9 +129,9 @@ class SparcAsmParser : public MCTargetAsmParser {
 
 public:
   SparcAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
-                const MCInstrInfo &MII,
-                const MCTargetOptions &Options)
-      : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
+                 const MCInstrInfo &MII, const MCTargetOptions &Options)
+      : MCTargetAsmParser(Options, sti, MII), Parser(parser),
+        MRI(*Parser.getContext().getRegisterInfo()) {
     Parser.addAliasForDirective(".half", ".2byte");
     Parser.addAliasForDirective(".uahalf", ".2byte");
     Parser.addAliasForDirective(".word", ".4byte");
@@ -156,16 +157,6 @@ class SparcAsmParser : public MCTargetAsmParser {
     Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
     Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
 
-  static const MCPhysReg FloatRegs[32] = {
-    Sparc::F0,  Sparc::F1,  Sparc::F2,  Sparc::F3,
-    Sparc::F4,  Sparc::F5,  Sparc::F6,  Sparc::F7,
-    Sparc::F8,  Sparc::F9,  Sparc::F10, Sparc::F11,
-    Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
-    Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
-    Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
-    Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
-    Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
-
   static const MCPhysReg DoubleRegs[32] = {
     Sparc::D0,  Sparc::D1,  Sparc::D2,  Sparc::D3,
     Sparc::D4,  Sparc::D5,  Sparc::D6,  Sparc::D7,
@@ -182,32 +173,12 @@ class SparcAsmParser : public MCTargetAsmParser {
     Sparc::Q8,  Sparc::Q9,  Sparc::Q10, Sparc::Q11,
     Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
 
-  static const MCPhysReg ASRRegs[32] = {
-    SP::Y,     SP::ASR1,  SP::ASR2,  SP::ASR3,
-    SP::ASR4,  SP::ASR5,  SP::ASR6, SP::ASR7,
-    SP::ASR8,  SP::ASR9,  SP::ASR10, SP::ASR11,
-    SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
-    SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
-    SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
-    SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
-    SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
-
   static const MCPhysReg IntPairRegs[] = {
     Sparc::G0_G1, Sparc::G2_G3, Sparc::G4_G5, Sparc::G6_G7,
     Sparc::O0_O1, Sparc::O2_O3, Sparc::O4_O5, Sparc::O6_O7,
     Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7,
     Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7};
 
-  static const MCPhysReg CoprocRegs[32] = {
-    Sparc::C0,  Sparc::C1,  Sparc::C2,  Sparc::C3,
-    Sparc::C4,  Sparc::C5,  Sparc::C6,  Sparc::C7,
-    Sparc::C8,  Sparc::C9,  Sparc::C10, Sparc::C11,
-    Sparc::C12, Sparc::C13, Sparc::C14, Sparc::C15,
-    Sparc::C16, Sparc::C17, Sparc::C18, Sparc::C19,
-    Sparc::C20, Sparc::C21, Sparc::C22, Sparc::C23,
-    Sparc::C24, Sparc::C25, Sparc::C26, Sparc::C27,
-    Sparc::C28, Sparc::C29, Sparc::C30, Sparc::C31 };
-
   static const MCPhysReg CoprocPairRegs[] = {
     Sparc::C0_C1,   Sparc::C2_C3,   Sparc::C4_C5,   Sparc::C6_C7,
     Sparc::C8_C9,   Sparc::C10_C11, Sparc::C12_C13, Sparc::C14_C15,
@@ -1325,313 +1296,146 @@ ParseStatus SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
   return ParseStatus::Success;
 }
 
-bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, MCRegister &RegNo,
+#define GET_REGISTER_MATCHER
+#include "SparcGenAsmMatcher.inc"
+
+bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, MCRegister &Reg,
                                        unsigned &RegKind) {
-  int64_t intVal = 0;
-  RegNo = 0;
+  Reg = SP::NoRegister;
   RegKind = SparcOperand::rk_None;
-  if (Tok.is(AsmToken::Identifier)) {
-    StringRef name = Tok.getString();
-
-    // %fp
-    if (name.equals("fp")) {
-      RegNo = Sparc::I6;
-      RegKind = SparcOperand::rk_IntReg;
-      return true;
-    }
-    // %sp
-    if (name.equals("sp")) {
-      RegNo = Sparc::O6;
-      RegKind = SparcOperand::rk_IntReg;
-      return true;
-    }
-
-    if (name.equals("y")) {
-      RegNo = Sparc::Y;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-
-    if (name.starts_with_insensitive("asr") &&
-        !name.substr(3).getAsInteger(10, intVal) && intVal > 0 && intVal < 32) {
-      RegNo = ASRRegs[intVal];
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-
-    if (name.equals("fprs")) {
-      RegNo = Sparc::ASR6;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
+  if (!Tok.is(AsmToken::Identifier))
+    return false;
 
-    if (name.equals("icc")) {
-      RegNo = Sparc::ICC;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
+  StringRef Name = Tok.getString();
+  Reg = MatchRegisterName(Name.lower());
+  if (!Reg)
+    Reg = MatchRegisterAltName(Name.lower());
 
-    if (name.equals("psr")) {
-      RegNo = Sparc::PSR;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
+  if (Reg) {
+    // Some registers have identical spellings. The generated matcher might
+    // have chosen one or another spelling, e.g. "%fp" or "%i6" might have been
+    // matched to either SP::I6 or SP::I6_I7. Other parts of SparcAsmParser
+    // are not prepared for this, so we do some canonicalization.
 
-    if (name.equals("fsr")) {
-      RegNo = Sparc::FSR;
+    // See the note in SparcRegisterInfo.td near ASRRegs register class.
+    if (Reg == SP::ASR4 && Name == "tick") {
+      Reg = SP::TICK;
       RegKind = SparcOperand::rk_Special;
       return true;
     }
 
-    if (name.equals("fq")) {
-      RegNo = Sparc::FQ;
-      RegKind = SparcOperand::rk_Special;
+    if (MRI.getRegClass(SP::IntRegsRegClassID).contains(Reg)) {
+      RegKind = SparcOperand::rk_IntReg;
       return true;
     }
-
-    if (name.equals("csr")) {
-      RegNo = Sparc::CPSR;
-      RegKind = SparcOperand::rk_Special;
+    if (MRI.getRegClass(SP::FPRegsRegClassID).contains(Reg)) {
+      RegKind = SparcOperand::rk_FloatReg;
       return true;
     }
-
-    if (name.equals("cq")) {
-      RegNo = Sparc::CPQ;
-      RegKind = SparcOperand::rk_Special;
+    if (MRI.getRegClass(SP::CoprocRegsRegClassID).contains(Reg)) {
+      RegKind = SparcOperand::rk_CoprocReg;
       return true;
     }
 
-    if (name.equals("wim")) {
-      RegNo = Sparc::WIM;
-      RegKind = SparcOperand::rk_Special;
+    // Canonicalize G0_G1 ... G30_G31 etc. to G0 ... G30.
+    if (MRI.getRegClass(SP::IntPairRegClassID).contains(Reg)) {
+      Reg = MRI.getSubReg(Reg, SP::sub_even);
+      RegKind = SparcOperand::rk_IntReg;
       return true;
     }
 
-    if (name.equals("tbr")) {
-      RegNo = Sparc::TBR;
-      RegKind = SparcOperand::rk_Special;
+    // Canonicalize D0 ... D15 to F0 ... F30.
+    if (MRI.getRegClass(SP::DFPRegsRegClassID).contains(Reg)) {
+      // D16 ... D31 do not have sub-registers.
+      if (MCRegister SubReg = MRI.getSubReg(Reg, SP::sub_even)) {
+        Reg = SubReg;
+        RegKind = SparcOperand::rk_FloatReg;
+        return true;
+      }
+      RegKind = SparcOperand::rk_DoubleReg;
       return true;
     }
+    
+    // The generated matcher does not currently return QFP registers.
+    // If it changes, we will need to handle them in a similar way.
+    assert(!MRI.getRegClass(SP::QFPRegsRegClassID).contains(Reg));
 
-    if (name.equals("xcc")) {
-      // FIXME:: check 64bit.
-      RegNo = Sparc::ICC;
-      RegKind = SparcOperand::rk_Special;
+    // Canonicalize C0_C1 ... C30_C31 to C0 ... C30.
+    if (MRI.getRegClass(SP::CoprocPairRegClassID).contains(Reg)) {
+      Reg = MRI.getSubReg(Reg, SP::sub_even);
+      RegKind = SparcOperand::rk_CoprocReg;
       return true;
     }
 
-    // %fcc0 - %fcc3
-    if (name.starts_with_insensitive("fcc") &&
-        !name.substr(3).getAsInteger(10, intVal) && intVal < 4) {
-      // FIXME: check 64bit and  handle %fcc1 - %fcc3
-      RegNo = Sparc::FCC0 + intVal;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
+    // Other registers do not need special handling.
+    assert(Reg && "Register lost during canonicalization");
+    RegKind = SparcOperand::rk_Special;
+    return true;
+  }
 
-    // %g0 - %g7
-    if (name.starts_with_insensitive("g") &&
-        !name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
-      RegNo = IntRegs[intVal];
-      RegKind = SparcOperand::rk_IntReg;
-      return true;
-    }
-    // %o0 - %o7
-    if (name.starts_with_insensitive("o") &&
-        !name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
-      RegNo = IntRegs[8 + intVal];
-      RegKind = SparcOperand::rk_IntReg;
-      return true;
-    }
-    if (name.starts_with_insensitive("l") &&
-        !name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
-      RegNo = IntRegs[16 + intVal];
-      RegKind = SparcOperand::rk_IntReg;
-      return true;
-    }
-    if (name.starts_with_insensitive("i") &&
-        !name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
-      RegNo = IntRegs[24 + intVal];
-      RegKind = SparcOperand::rk_IntReg;
-      return true;
-    }
-    // %f0 - %f31
-    if (name.starts_with_insensitive("f") &&
-        !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
-      RegNo = FloatRegs[intVal];
-      RegKind = SparcOperand::rk_FloatReg;
-      return true;
-    }
-    // %f32 - %f62
-    if (name.starts_with_insensitive("f") &&
-        !name.substr(1, 2).getAsInteger(10, intVal) && intVal >= 32 &&
-        intVal <= 62 && (intVal % 2 == 0)) {
-      // FIXME: Check V9
-      RegNo = DoubleRegs[intVal/2];
-      RegKind = SparcOperand::rk_DoubleReg;
-      return true;
-    }
+  // If we still have no match, try custom parsing.
+  // Not all registers and their spellings are modeled in td files.
 
-    // %r0 - %r31
-    if (name.starts_with_insensitive("r") &&
-        !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
-      RegNo = IntRegs[intVal];
-      RegKind = SparcOperand::rk_IntReg;
-      return true;
-    }
+  // %r0 - %r31
+  int64_t RegNo = 0;
+  if (Name.starts_with_insensitive("r") &&
+      !Name.substr(1, 2).getAsInteger(10, RegNo) && RegNo < 31) {
+    Reg = IntRegs[RegNo];
+    RegKind = SparcOperand::rk_IntReg;
+    return true;
+  }
 
-    // %c0 - %c31
-    if (name.starts_with_insensitive("c") &&
-        !name.substr(1).getAsInteger(10, intVal) && intVal < 32) {
-      RegNo = CoprocRegs[intVal];
-      RegKind = SparcOperand::rk_CoprocReg;
-      return true;
-    }
+  if (Name.equals("xcc")) {
+    // FIXME:: check 64bit.
+    Reg = SP::ICC;
+    RegKind = SparcOperand::rk_Special;
+    return true;
+  }
 
-    if (name.equals("tpc")) {
-      RegNo = Sparc::TPC;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("tnpc")) {
-      RegNo = Sparc::TNPC;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("tstate")) {
-      RegNo = Sparc::TSTATE;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("tt")) {
-      RegNo = Sparc::TT;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("tick")) {
-      RegNo = Sparc::TICK;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("tba")) {
-      RegNo = Sparc::TBA;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("pstate")) {
-      RegNo = Sparc::PSTATE;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("tl")) {
-      RegNo = Sparc::TL;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("pil")) {
-      RegNo = Sparc::PIL;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("cwp")) {
-      RegNo = Sparc::CWP;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("cansave")) {
-      RegNo = Sparc::CANSAVE;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("canrestore")) {
-      RegNo = Sparc::CANRESTORE;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("cleanwin")) {
-      RegNo = Sparc::CLEANWIN;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("otherwin")) {
-      RegNo = Sparc::OTHERWIN;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("wstate")) {
-      RegNo = Sparc::WSTATE;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("pc")) {
-      RegNo = Sparc::ASR5;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("asi")) {
-      RegNo = Sparc::ASR3;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("ccr")) {
-      RegNo = Sparc::ASR2;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("gl")) {
-      RegNo = Sparc::GL;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("ver")) {
-      RegNo = Sparc::VER;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
+  // JPS1 extension - aliases for ASRs
+  // Section A.51 - Read State Register
+  if (Name.equals("pcr")) {
+    Reg = SP::ASR16;
+    RegKind = SparcOperand::rk_Special;
+    return true;
+  }
 
-    // JPS1 extension - aliases for ASRs
-    // Section A.51 - Read State Register
-    if (name.equals("pcr")) {
-      RegNo = Sparc::ASR16;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("pic")) {
-      RegNo = Sparc::ASR17;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("dcr")) {
-      RegNo = Sparc::ASR18;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("gsr")) {
-      RegNo = Sparc::ASR19;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("softint")) {
-      RegNo = Sparc::ASR22;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("tick_cmpr")) {
-      RegNo = Sparc::ASR23;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("stick") || name.equals("sys_tick")) {
-      RegNo = Sparc::ASR24;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
-    if (name.equals("stick_cmpr") || name.equals("sys_tick_cmpr")) {
-      RegNo = Sparc::ASR25;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
+  if (Name.equals("pic")) {
+    Reg = SP::ASR17;
+    RegKind = SparcOperand::rk_Special;
+    return true;
+  }
+  if (Name.equals("dcr")) {
+    Reg = SP::ASR18;
+    RegKind = SparcOperand::rk_Special;
+    return true;
+  }
+  if (Name.equals("gsr")) {
+    Reg = SP::ASR19;
+    RegKind = SparcOperand::rk_Special;
+    return true;
+  }
+  if (Name.equals("softint")) {
+    Reg = SP::ASR22;
+    RegKind = SparcOperand::rk_Special;
+    return true;
   }
+  if (Name.equals("tick_cmpr")) {
+    Reg = SP::ASR23;
+    RegKind = SparcOperand::rk_Special;
+    return true;
+  }
+  if (Name.equals("stick") || Name.equals("sys_tick")) {
+    Reg = SP::ASR24;
+    RegKind = SparcOperand::rk_Special;
+    return true;
+  }
+  if (Name.equals("stick_cmpr") || Name.equals("sys_tick_cmpr")) {
+    Reg = SP::ASR25;
+    RegKind = SparcOperand::rk_Special;
+    return true;
+  }
+
   return false;
 }
 
@@ -1737,7 +1541,6 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcAsmParser() {
   RegisterMCAsmParser<SparcAsmParser> C(getTheSparcelTarget());
 }
 
-#define GET_REGISTER_MATCHER
 #define GET_MATCHER_IMPLEMENTATION
 #include "SparcGenAsmMatcher.inc"
 
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 38a59e650f33c7..45cf985cfa0627 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -99,7 +99,8 @@ include "SparcInstrInfo.td"
 def SparcInstrInfo : InstrInfo;
 
 def SparcAsmParser : AsmParser {
-  bit ShouldEmitMatchRegisterName = 0;
+  let ShouldEmitMatchRegisterAltName = true;
+  let AllowDuplicateRegisterNames = true;
 }
 
 def SparcAsmParserVariant : AsmParserVariant {

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[koachan]

The spec doc doesn't seem to specify it, but at least going by GCC behavior, dXX/qXX names use the same register number as fXX, just with extra validation.
For example:

• d0 = f0, d2 = f2, d4 = f4 etc.
• d1, d3, d5, etc. -> assembler error

[s-barannikov]

Currently, we only accept %f0 - %f63 as valid register names. If an odd-numbered register is used in an instruction expecting a double-fp register, a diagnostic is issued:

test.s:1:17: error: invalid operand for instruction
faddd %f0, %f0, %f1
                ^

Similarly, for quad-fp registers:

test.s:1:17: error: invalid operand for instruction
faddq %f0, %f0, %f2
                ^

I can try to support %d and %q mnemonics, but I'd prefer to do this in a separate patch (this patch is supposed to be NFC).

[koachan]

I see. I think all is okay then.