[RISCV] Use TImmLeaf for csr_sysreg

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -11734,14 +11734,14 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
     SDValue LoCounter, HiCounter;
     MVT XLenVT = Subtarget.getXLenVT();
     if (N->getOpcode() == ISD::READCYCLECOUNTER) {
-      LoCounter = DAG.getConstant(
+      LoCounter = DAG.getTargetConstant(
           RISCVSysReg::lookupSysRegByName("CYCLE")->Encoding, DL, XLenVT);
-      HiCounter = DAG.getConstant(
+      HiCounter = DAG.getTargetConstant(
           RISCVSysReg::lookupSysRegByName("CYCLEH")->Encoding, DL, XLenVT);
     } else {
-      LoCounter = DAG.getConstant(
+      LoCounter = DAG.getTargetConstant(
           RISCVSysReg::lookupSysRegByName("TIME")->Encoding, DL, XLenVT);
-      HiCounter = DAG.getConstant(
+      HiCounter = DAG.getTargetConstant(
           RISCVSysReg::lookupSysRegByName("TIMEH")->Encoding, DL, XLenVT);
     }
     SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);

llvm/lib/Target/RISCV/RISCVISelLowering.h

@@ -127,7 +127,8 @@ enum NodeType : unsigned {
   FMAX, FMIN,
 
   // A read of the 64-bit counter CSR on a 32-bit target (returns (Lo, Hi)).
-  // It takes a chain operand.
+  // It takes a chain operand and another two target constant operands (the
+  // CSR numbers of the low and high parts of the counter).
   READ_COUNTER_WIDE,
 
   // brev8, orc.b, zip, and unzip from Zbb and Zbkb. All operands are i32 or

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -365,7 +365,7 @@ def CSRSystemRegister : AsmOperandClass {
   let DiagnosticType = "InvalidCSRSystemRegister";
 }
 
-def csr_sysreg : RISCVOp, ImmLeaf<XLenVT, "return isUInt<12>(Imm);"> {
+def csr_sysreg : RISCVOp, TImmLeaf<XLenVT, "return isUInt<12>(Imm);"> {
   let ParserMatchClass = CSRSystemRegister;
   let PrintMethod = "printCSRSystemRegister";
   let DecoderMethod = "decodeUImmOperand<12>";