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[RISCV] Fix insert_subvector with fixed vector type creating invalid node #82975

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Merged
merged 1 commit into from
Feb 26, 2024
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[RISCV] Fix insert_subvector with fixed vector type creating invalid node #82975

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8 changes: 5 additions & 3 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2066,14 +2066,15 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
assert(Idx == 0 && V.isUndef());
SubVecContainerVT = TLI.getContainerForFixedLengthVector(SubVecVT);
}
MVT ContainerVT = VT;
if (VT.isFixedLengthVector())
VT = TLI.getContainerForFixedLengthVector(VT);
ContainerVT = TLI.getContainerForFixedLengthVector(VT);

const auto *TRI = Subtarget->getRegisterInfo();
unsigned SubRegIdx;
std::tie(SubRegIdx, Idx) =
RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
VT, SubVecContainerVT, Idx, TRI);
ContainerVT, SubVecContainerVT, Idx, TRI);

// If the Idx hasn't been completely eliminated then this is a subvector
// insert which doesn't naturally align to a vector register. These must
Expand All @@ -2093,7 +2094,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
// If we haven't set a SubRegIdx, then we must be going between
// equally-sized LMUL groups (e.g. VR -> VR). This can be done as a copy.
if (SubRegIdx == RISCV::NoSubRegister) {
unsigned InRegClassID = RISCVTargetLowering::getRegClassIDForVecVT(VT);
unsigned InRegClassID =
RISCVTargetLowering::getRegClassIDForVecVT(ContainerVT);
assert(RISCVTargetLowering::getRegClassIDForVecVT(SubVecContainerVT) ==
InRegClassID &&
"Unexpected subvector extraction");
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