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[AMDGPU] Only try DecoderTables for the current subtarget. NFCI. #82992

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Merged
merged 1 commit into from
Feb 26, 2024
Merged

[AMDGPU] Only try DecoderTables for the current subtarget. NFCI. #82992

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45 changes: 30 additions & 15 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -466,15 +466,18 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
if (isGFX11Plus() && Bytes.size() >= 12 ) {
DecoderUInt128 DecW = eat12Bytes(Bytes);

if (tryDecodeInst(DecoderTableGFX1196, DecoderTableGFX11_FAKE1696, MI,
if (isGFX11() &&
tryDecodeInst(DecoderTableGFX1196, DecoderTableGFX11_FAKE1696, MI,
DecW, Address, CS))
break;

if (tryDecodeInst(DecoderTableGFX1296, DecoderTableGFX12_FAKE1696, MI,
if (isGFX12() &&
tryDecodeInst(DecoderTableGFX1296, DecoderTableGFX12_FAKE1696, MI,
DecW, Address, CS))
break;

if (tryDecodeInst(DecoderTableGFX12W6496, MI, DecW, Address, CS))
if (isGFX12() &&
tryDecodeInst(DecoderTableGFX12W6496, MI, DecW, Address, CS))
break;
}

Expand Down Expand Up @@ -507,27 +510,32 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS))
break;

if (tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS))
if ((isVI() || isGFX9()) &&
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Historical wart: namespace "GFX8" is used for lots of instructions that are shared with GFX9. Perhaps it should be renamed to "GFX8GFX9" or split into a shared part and a GFX8-only part. But I didn't want to touch that in this patch.

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I think it would be better to have a common table for all sub targets with a shared encoding. That looks more like normal cpu targets, where you can emit instructions that will just fault on unsupported CPUs. Really we probably should be using different top level targets for each major encoding change

tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS))
break;

if (tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS))
if (isGFX9() && tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS))
break;

if (tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS))
if (isGFX10() && tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS))
break;

if (tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW,
if (isGFX12() &&
tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW,
Address, CS))
break;

if (tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW,
if (isGFX11() &&
tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW,
Address, CS))
break;

if (tryDecodeInst(DecoderTableGFX11W6464, MI, QW, Address, CS))
if (isGFX11() &&
tryDecodeInst(DecoderTableGFX11W6464, MI, QW, Address, CS))
break;

if (tryDecodeInst(DecoderTableGFX12W6464, MI, QW, Address, CS))
if (isGFX12() &&
tryDecodeInst(DecoderTableGFX12W6464, MI, QW, Address, CS))
break;
}

Expand All @@ -538,13 +546,14 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
if (Bytes.size() >= 4) {
const uint32_t DW = eatBytes<uint32_t>(Bytes);

if (tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS))
if ((isVI() || isGFX9()) &&
tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS))
break;

if (tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS))
break;

if (tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS))
if (isGFX9() && tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS))
break;

if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts) &&
Expand All @@ -555,14 +564,16 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS))
break;

if (tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS))
if (isGFX10() && tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS))
break;

if (tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW,
if (isGFX11() &&
tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW,
Address, CS))
break;

if (tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW,
if (isGFX12() &&
tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW,
Address, CS))
break;
}
Expand Down Expand Up @@ -1750,6 +1761,10 @@ bool AMDGPUDisassembler::isGFX11Plus() const {
return AMDGPU::isGFX11Plus(STI);
}

bool AMDGPUDisassembler::isGFX12() const {
return STI.hasFeature(AMDGPU::FeatureGFX12);
}

bool AMDGPUDisassembler::isGFX12Plus() const {
return AMDGPU::isGFX12Plus(STI);
}
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
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Original file line number Diff line number Diff line change
Expand Up @@ -275,6 +275,7 @@ class AMDGPUDisassembler : public MCDisassembler {
bool isGFX10Plus() const;
bool isGFX11() const;
bool isGFX11Plus() const;
bool isGFX12() const;
bool isGFX12Plus() const;

bool hasArchitectedFlatScratch() const;
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/MIMGInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -527,7 +527,7 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
let ssamp = 0 in {
if op.HAS_GFX10M then {
def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32,
!if(enableDisasm, "GFX10", "")>;
!if(enableDisasm, "GFX8", "")>;
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This is fixing a mistake that was previously harmless because we tried all namespaces on all subtargets.

if !not(ExtendedImageInst) then
def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPR_32,
!if(enableDisasm, "GFX90A", "")>;
Expand Down Expand Up @@ -754,7 +754,7 @@ multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm,
let ssamp = 0 in {
if op.HAS_GFX10M then {
def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32,
!if(enableDisasm, "GFX10", "")>;
!if(enableDisasm, "GFX8", "")>;
let hasPostISelHook = 1 in
def _V1_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VGPR_32,
!if(enableDisasm, "GFX90A", "")>;
Expand Down Expand Up @@ -1298,7 +1298,7 @@ multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
if op.HAS_GFX10M then {
def _V # addr.NumWords
: MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass,
!if(!and(enableDisasm, addr.Disassemble), "GFX10", "")>;
!if(!and(enableDisasm, addr.Disassemble), "GFX8", "")>;
if !not(ExtendedImageInst) then
def _V # addr.NumWords # _gfx90a
: MIMG_Sampler_gfx90a <op, asm, dst_rc, addr.RegClass,
Expand Down