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[RISCV] Add the CSR names from Smrnmi. #83370

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Merged
merged 1 commit into from
Mar 20, 2024
Merged

[RISCV] Add the CSR names from Smrnmi. #83370

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1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -108,6 +108,7 @@ Changes to the RISC-V Backend
* The experimental Ssnpm, Smnpm, Smmpm, Sspm, and Supm 0.8.1 Pointer Masking extensions are supported.
* The experimental Ssqosid extension is supported.
* Zacas is no longer experimental.
* Added the CSR names from the Resumable Non-Maskable Interrupts (Smrnmi) extension.

Changes to the WebAssembly Backend
----------------------------------
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9 changes: 9 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSystemOperands.td
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Expand Up @@ -418,7 +418,16 @@ def : SysReg<"vsieh", 0x214>;
def : SysReg<"vsiph", 0x254>;
} // isRV32Only

//===-----------------------------------------------
// Jump Vector Table CSR
//===-----------------------------------------------

def : SysReg<"jvt", 0x017>;

//===-----------------------------------------------
// Resumable Non-Maskable Interrupts(Smrnmi) CSRs
//===-----------------------------------------------
def : SysReg<"mnscratch", 0x740>;
def : SysReg<"mnepc", 0x741>;
def : SysReg<"mncause", 0x742>;
def : SysReg<"mnstatus", 0x744>;
56 changes: 56 additions & 0 deletions llvm/test/MC/RISCV/rv32-machine-csr-names.s
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Expand Up @@ -1149,3 +1149,59 @@ csrrs t2, 0x319, zero
csrrs t1, miph, zero
# uimm12
csrrs t2, 0x354, zero

################################################
# Resumable Non-Maskable Interrupts(Smrnmi) CSRs
################################################

# mnscratch
# name
# CHECK-INST: csrrs t1, mnscratch, zero
# CHECK-ENC: encoding: [0x73,0x23,0x00,0x74]
# CHECK-INST-ALIAS: csrr t1, mnscratch
# uimm12
# CHECK-INST: csrrs t2, mnscratch, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x74]
# CHECK-INST-ALIAS: csrr t2, mnscratch
csrrs t1, mnscratch, zero
# uimm12
csrrs t2, 0x740, zero

# mnepc
# name
# CHECK-INST: csrrs t1, mnepc, zero
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x74]
# CHECK-INST-ALIAS: csrr t1, mnepc
# uimm12
# CHECK-INST: csrrs t2, mnepc, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x74]
# CHECK-INST-ALIAS: csrr t2, mnepc
csrrs t1, mnepc, zero
# uimm12
csrrs t2, 0x741, zero

# mncause
# name
# CHECK-INST: csrrs t1, mncause, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x74]
# CHECK-INST-ALIAS: csrr t1, mncause
# uimm12
# CHECK-INST: csrrs t2, mncause, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x74]
# CHECK-INST-ALIAS: csrr t2, mncause
csrrs t1, mncause, zero
# uimm12
csrrs t2, 0x742, zero

# mnstatus
# name
# CHECK-INST: csrrs t1, mnstatus, zero
# CHECK-ENC: encoding: [0x73,0x23,0x40,0x74]
# CHECK-INST-ALIAS: csrr t1, mnstatus
# uimm12
# CHECK-INST: csrrs t2, mnstatus, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x74]
# CHECK-INST-ALIAS: csrr t2, mnstatus
csrrs t1, mnstatus, zero
# uimm12
csrrs t2, 0x744, zero