[Hexagon] Fix shift value when folding shl DAG node

[yandalur]

When folding (or (shl xx, s), (zext y)) to (COMBINE (shl xx, s-32), y), fix resulting shift value in HexagonISD::COMBINE node to not generate negative values.

[yandalur]

@iajbar @SundeepKushwaha Could you please help review this patch?

[iajbar]

If allocated registers change, this check will fail.
; CHECK-NEXT: r2 = addasl(r2,r1,#1)
; CHECK-NEXT: r3 = asl(r1,#1)
What about using: r[[REG1:[0-9]+]] and r[[REG2:[0-9]+]] instead?

[yandalur]

Used regex for register numbers. I have kept the argument registers in the test.

[iajbar]

Does the test need to have:
attributes #0 = { nofree nosync nounwind memory(readwrite, inaccessiblemem: none) "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv71" "target-features"="+v71,-long-calls" }

!llvm.module.flags = !{!0, !1}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 7, !"frame-pointer", i32 2}
!2 = !{!3, !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"}

I think you can remove it.

[yandalur]

Removed these attributes from the test