Skip to content

[DAGCombiner] Handle extending EXTRACT_VECTOR_ELTs in calculateByteProvider #83963

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Mar 5, 2024
Merged

[DAGCombiner] Handle extending EXTRACT_VECTOR_ELTs in calculateByteProvider #83963

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
e34658b
[DAGCombiner] Handle extending EXTRACT_VECTOR_ELTs in calculateBytePr…
lukel97 Mar 5, 2024
3cf1b40
Name variables, drop -verify-machineinstrs
lukel97 Mar 5, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8627,6 +8627,10 @@ calculateByteProvider(SDValue Op, unsigned Index, unsigned Depth,
if (NarrowBitWidth % 8 != 0)
return std::nullopt;
uint64_t NarrowByteWidth = NarrowBitWidth / 8;
// EXTRACT_VECTOR_ELT can extend the element type to the width of the return
// type, leaving the high bits undefined.
if (Index >= NarrowByteWidth)
return std::nullopt;

// Check to see if the position of the element in the vector corresponds
// with the byte we are trying to provide for. In the case of a vector of
Expand Down
16 changes: 16 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/pr83920.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s

define i8 @or_load_combine(ptr %p) {
; CHECK-LABEL: or_load_combine:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ori a0, a0, 1
; CHECK-NEXT: ret
%load = load <2 x i8>, ptr %p
%extract = extractelement <2 x i8> %load, i64 0
%or = or i8 %extract, 1
ret i8 %or
}