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[RISCV] Slightly improve expanded multiply emulation in getVLENFactoredAmount. #84113

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merged 2 commits into from
Mar 6, 2024
Merged

[RISCV] Slightly improve expanded multiply emulation in getVLENFactoredAmount. #84113

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a378ed5
[RISCV] Slightly improve expanded multiply emulation in getVLENFactor…
topperc Mar 6, 2024
268b6e9
fixup! Use COPY.
topperc Mar 6, 2024
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28 changes: 17 additions & 11 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3130,11 +3130,7 @@ void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
.addReg(N, RegState::Kill)
.setMIFlag(Flag);
} else {
Register Acc = MRI.createVirtualRegister(&RISCV::GPRRegClass);
BuildMI(MBB, II, DL, get(RISCV::ADDI), Acc)
.addReg(RISCV::X0)
.addImm(0)
.setMIFlag(Flag);
Register Acc;
uint32_t PrevShiftAmount = 0;
for (uint32_t ShiftAmount = 0; NumOfVReg >> ShiftAmount; ShiftAmount++) {
if (NumOfVReg & (1U << ShiftAmount)) {
Expand All @@ -3143,17 +3139,27 @@ void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
.addReg(DestReg, RegState::Kill)
.addImm(ShiftAmount - PrevShiftAmount)
.setMIFlag(Flag);
if (NumOfVReg >> (ShiftAmount + 1))
BuildMI(MBB, II, DL, get(RISCV::ADD), Acc)
.addReg(Acc, RegState::Kill)
.addReg(DestReg)
.setMIFlag(Flag);
if (NumOfVReg >> (ShiftAmount + 1)) {
// If we don't have an accmulator yet, create it and copy DestReg.
if (!Acc) {
Acc = MRI.createVirtualRegister(&RISCV::GPRRegClass);
BuildMI(MBB, II, DL, get(TargetOpcode::COPY), Acc)
.addReg(DestReg)
.setMIFlag(Flag);
} else {
BuildMI(MBB, II, DL, get(RISCV::ADD), Acc)
.addReg(Acc, RegState::Kill)
.addReg(DestReg)
.setMIFlag(Flag);
}
}
PrevShiftAmount = ShiftAmount;
}
}
assert(Acc && "Expected valid accumulator");
BuildMI(MBB, II, DL, get(RISCV::ADD), DestReg)
.addReg(DestReg, RegState::Kill)
.addReg(Acc)
.addReg(Acc, RegState::Kill)
.setMIFlag(Flag);
}
}
Expand Down
9 changes: 3 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
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Expand Up @@ -253,9 +253,8 @@ define void @lmul4_and_2_x2_1() nounwind {
; NOMUL-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; NOMUL-NEXT: addi s0, sp, 48
; NOMUL-NEXT: csrr a0, vlenb
; NOMUL-NEXT: li a1, 0
; NOMUL-NEXT: slli a0, a0, 2
; NOMUL-NEXT: add a1, a1, a0
; NOMUL-NEXT: mv a1, a0
; NOMUL-NEXT: slli a0, a0, 1
; NOMUL-NEXT: add a0, a0, a1
; NOMUL-NEXT: sub sp, sp, a0
Expand Down Expand Up @@ -455,9 +454,8 @@ define void @lmul_8_x5() nounwind {
; NOMUL-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; NOMUL-NEXT: addi s0, sp, 80
; NOMUL-NEXT: csrr a0, vlenb
; NOMUL-NEXT: li a1, 0
; NOMUL-NEXT: slli a0, a0, 3
; NOMUL-NEXT: add a1, a1, a0
; NOMUL-NEXT: mv a1, a0
; NOMUL-NEXT: slli a0, a0, 2
; NOMUL-NEXT: add a0, a0, a1
; NOMUL-NEXT: sub sp, sp, a0
Expand Down Expand Up @@ -517,9 +515,8 @@ define void @lmul_8_x9() nounwind {
; NOMUL-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; NOMUL-NEXT: addi s0, sp, 80
; NOMUL-NEXT: csrr a0, vlenb
; NOMUL-NEXT: li a1, 0
; NOMUL-NEXT: slli a0, a0, 3
; NOMUL-NEXT: add a1, a1, a0
; NOMUL-NEXT: mv a1, a0
; NOMUL-NEXT: slli a0, a0, 3
; NOMUL-NEXT: add a0, a0, a1
; NOMUL-NEXT: sub sp, sp, a0
Expand Down
24 changes: 8 additions & 16 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
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Expand Up @@ -2133,9 +2133,8 @@ define float @vreduce_fminimum_v128f32(ptr %x) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
Expand Down Expand Up @@ -2256,9 +2255,8 @@ define float @vreduce_fminimum_v128f32(ptr %x) {
; CHECK-NEXT: vfmin.vv v8, v11, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 0
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
Expand Down Expand Up @@ -2739,9 +2737,8 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
Expand Down Expand Up @@ -2852,9 +2849,8 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; CHECK-NEXT: vfmin.vv v8, v11, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 0
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
Expand Down Expand Up @@ -3461,9 +3457,8 @@ define float @vreduce_fmaximum_v128f32(ptr %x) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
Expand Down Expand Up @@ -3584,9 +3579,8 @@ define float @vreduce_fmaximum_v128f32(ptr %x) {
; CHECK-NEXT: vfmax.vv v8, v11, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 0
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
Expand Down Expand Up @@ -4067,9 +4061,8 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
Expand Down Expand Up @@ -4180,9 +4173,8 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; CHECK-NEXT: vfmax.vv v8, v11, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 0
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
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Expand Up @@ -193,9 +193,8 @@ define <32 x i32> @concat_8xv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x
; VLA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; VLA-NEXT: vmv1r.v v16, v15
; VLA-NEXT: csrr a0, vlenb
; VLA-NEXT: li a1, 0
; VLA-NEXT: slli a0, a0, 3
; VLA-NEXT: add a1, a1, a0
; VLA-NEXT: mv a1, a0
; VLA-NEXT: slli a0, a0, 1
; VLA-NEXT: add a0, a0, a1
; VLA-NEXT: add a0, sp, a0
Expand Down Expand Up @@ -245,9 +244,8 @@ define <32 x i32> @concat_8xv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x
; VLA-NEXT: li a0, 32
; VLA-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; VLA-NEXT: csrr a0, vlenb
; VLA-NEXT: li a1, 0
; VLA-NEXT: slli a0, a0, 3
; VLA-NEXT: add a1, a1, a0
; VLA-NEXT: mv a1, a0
; VLA-NEXT: slli a0, a0, 1
; VLA-NEXT: add a0, a0, a1
; VLA-NEXT: add a0, sp, a0
Expand Down