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AMDGPI: Rename HasExpOrExportInsts to HasExportInsts. NFC #84252

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Merged
merged 1 commit into from
Mar 6, 2024
Merged

AMDGPI: Rename HasExpOrExportInsts to HasExportInsts. NFC #84252

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPU.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1881,7 +1881,7 @@ def D16PreservesUnusedBits :
def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;

def HasExpOrExportInsts : Predicate<"Subtarget->hasExpOrExportInsts()">,
def HasExportInsts : Predicate<"Subtarget->hasExportInsts()">,
AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;

def HasInterpInsts : Predicate<"Subtarget->hasInterpInsts()">,
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6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/EXPInstructions.td
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Expand Up @@ -58,12 +58,12 @@ class EXP_Real_Row<string pseudo, int subtarget, string name = "exp", EXP_Pseudo

// DONE variants have mayLoad = 1.
// ROW variants have an implicit use of M0.
let SubtargetPredicate = HasExpOrExportInsts in {
let SubtargetPredicate = HasExportInsts in {
def EXP : EXP_Pseudo<0, 0>;
def EXP_DONE : EXP_Pseudo<0, 1>;
def EXP_ROW : EXP_Pseudo<1, 0>;
def EXP_ROW_DONE : EXP_Pseudo<1, 1>;
} // let SubtargetPredicate = HasExpOrExportInsts
} // let SubtargetPredicate = HasExportInsts

//===----------------------------------------------------------------------===//
// SI, VI, GFX10.
Expand Down Expand Up @@ -117,7 +117,7 @@ multiclass EXP_Real_gfx11 {
multiclass VEXPORT_Real_gfx12 {
defvar ps = !cast<EXP_Pseudo>(NAME);
def _gfx12 : EXP_Real_Row<NAME, SIEncodingFamily.GFX12, "export">,
EXPe_Row, MnemonicAlias<"exp", "export">, Requires<[isGFX12Plus, HasExpOrExportInsts]> {
EXPe_Row, MnemonicAlias<"exp", "export">, Requires<[isGFX12Plus, HasExportInsts]> {
let AssemblerPredicate = isGFX12Only;
let DecoderNamespace = "GFX12";
let row = ps.row;
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/GCNSubtarget.h
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Expand Up @@ -648,7 +648,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
// BUFFER/FLAT/GLOBAL_ATOMIC_ADD/MIN/MAX_F64
bool hasBufferFlatGlobalAtomicsF64() const { return hasGFX90AInsts(); }

bool hasExpOrExportInsts() const {
bool hasExportInsts() const {
return !hasGFX940Insts();
}

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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SOPInstructions.td
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Expand Up @@ -1705,7 +1705,7 @@ let SubtargetPredicate = isGFX10Plus in {
} // End SubtargetPredicate = isGFX10Plus

let SubtargetPredicate = isGFX11Plus in {
let OtherPredicates = [HasExpOrExportInsts] in
let OtherPredicates = [HasExportInsts] in
def S_WAIT_EVENT : SOPP_Pseudo<"s_wait_event", (ins s16imm:$simm16),
"$simm16"> {
let hasSideEffects = 1;
Expand Down Expand Up @@ -1738,7 +1738,7 @@ let OtherPredicates = [HasImageInsts] in {
SOPP_Pseudo<"s_wait_bvhcnt", (ins s16imm:$simm16), "$simm16",
[(int_amdgcn_s_wait_bvhcnt timm:$simm16)]>;
} // End OtherPredicates = [HasImageInsts].
let OtherPredicates = [HasExpOrExportInsts] in
let OtherPredicates = [HasExportInsts] in
def S_WAIT_EXPCNT :
SOPP_Pseudo<"s_wait_expcnt", (ins s16imm:$simm16), "$simm16",
[(int_amdgcn_s_wait_expcnt timm:$simm16)]>;
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