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[RISCV][NFC] Add generateMCInstSeq in RISCVMatInt #84462

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Merged
merged 4 commits into from
Mar 22, 2024
Merged

[RISCV][NFC] Add generateMCInstSeq in RISCVMatInt #84462

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18f03c9
Add generateMCInstSeq in RISCVMatInt
Zeavee Mar 8, 2024
cd38586
Replace SmallVector by SmallVectorImpl and pass it in the parameters
Zeavee Mar 8, 2024
3b2524c
Remove MCInst import
Zeavee Mar 8, 2024
6f5a41f
Replace MCRegisterInfo import by MCRegister
Zeavee Mar 11, 2024
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31 changes: 4 additions & 27 deletions llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3081,34 +3081,11 @@ void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {

void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
MCStreamer &Out) {
RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Value, getSTI());

MCRegister SrcReg = RISCV::X0;
for (const RISCVMatInt::Inst &Inst : Seq) {
switch (Inst.getOpndKind()) {
case RISCVMatInt::Imm:
emitToStreamer(Out,
MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addImm(Inst.getImm()));
break;
case RISCVMatInt::RegX0:
emitToStreamer(
Out, MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addReg(SrcReg).addReg(
RISCV::X0));
break;
case RISCVMatInt::RegReg:
emitToStreamer(
Out, MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addReg(SrcReg).addReg(
SrcReg));
break;
case RISCVMatInt::RegImm:
emitToStreamer(
Out, MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addReg(SrcReg).addImm(
Inst.getImm()));
break;
}
SmallVector<MCInst, 8> Seq;
RISCVMatInt::generateMCInstSeq(Value, getSTI(), DestReg, Seq);

// Only the first instruction has X0 as its source.
SrcReg = DestReg;
for (MCInst &Inst : Seq) {
emitToStreamer(Out, Inst);
}
}

Expand Down
38 changes: 38 additions & 0 deletions llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
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Expand Up @@ -9,6 +9,7 @@
#include "RISCVMatInt.h"
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "llvm/ADT/APInt.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/Support/MathExtras.h"
using namespace llvm;

Expand Down Expand Up @@ -436,6 +437,43 @@ InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI) {
return Res;
}

void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI,
MCRegister DestReg, SmallVectorImpl<MCInst> &Insts) {
RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val, STI);

MCRegister SrcReg = RISCV::X0;
for (RISCVMatInt::Inst &Inst : Seq) {
switch (Inst.getOpndKind()) {
case RISCVMatInt::Imm:
Insts.push_back(MCInstBuilder(Inst.getOpcode())
.addReg(DestReg)
.addImm(Inst.getImm()));
break;
case RISCVMatInt::RegX0:
Insts.push_back(MCInstBuilder(Inst.getOpcode())
.addReg(DestReg)
.addReg(SrcReg)
.addReg(RISCV::X0));
break;
case RISCVMatInt::RegReg:
Insts.push_back(MCInstBuilder(Inst.getOpcode())
.addReg(DestReg)
.addReg(SrcReg)
.addReg(SrcReg));
break;
case RISCVMatInt::RegImm:
Insts.push_back(MCInstBuilder(Inst.getOpcode())
.addReg(DestReg)
.addReg(SrcReg)
.addImm(Inst.getImm()));
break;
}

// Only the first instruction has X0 as its source.
SrcReg = DestReg;
}
}

InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI,
unsigned &ShiftAmt, unsigned &AddOpc) {
int64_t LoVal = SignExtend64<32>(Val);
Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
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Expand Up @@ -10,6 +10,7 @@
#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H

#include "llvm/ADT/SmallVector.h"
#include "llvm/MC/MCRegister.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include <cstdint>

Expand Down Expand Up @@ -48,6 +49,10 @@ using InstSeq = SmallVector<Inst, 8>;
// instruction selection.
InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI);

// Helper to generate the generateInstSeq instruction sequence using MCInsts
void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI,
MCRegister DestReg, SmallVectorImpl<MCInst> &Insts);

// Helper to generate an instruction sequence that can materialize the given
// immediate value into a register using an additional temporary register. This
// handles cases where the constant can be generated by (ADD (SLLI X, C), X) or
Expand Down