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[RISCV] Add integer RISCVISD::SELECT_CC to canCreateUndefOrPoison and isGuaranteedNotToBeUndefOrPoison. #84693

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Merged
merged 5 commits into from
Mar 25, 2024
Merged

[RISCV] Add integer RISCVISD::SELECT_CC to canCreateUndefOrPoison and isGuaranteedNotToBeUndefOrPoison. #84693

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70bf7c4
[RISCV] Add integer RISCVISD::SELECT_CC to canCreateUndefOrPoison and…
topperc Mar 10, 2024
0fcaf2e
fixup! Add check for integer type to isGuaranteedNotToBeUndefOrPoison…
topperc Mar 11, 2024
6cea972
fixup! Add a generic implementation of isGuaranteedNotToBeUndefOrPois…
topperc Mar 21, 2024
b7b4785
fixup! clang-format
topperc Mar 21, 2024
deafeda
Merge remote-tracking branch 'origin/main' into pr/select-cc-poison
topperc Mar 21, 2024
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17 changes: 17 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -17029,6 +17029,23 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
return 1;
}

bool RISCVTargetLowering::canCreateUndefOrPoisonForTargetNode(
SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const {

// TODO: Add more target nodes.
switch (Op.getOpcode()) {
case RISCVISD::SELECT_CC:
// Integer select_cc cannot create poison.
// TODO: What are the FP poison semantics?
// TODO: This instruction blocks poison from the unselected operand, can
// we do anything with that?
return !Op.getValueType().isInteger();
}
return TargetLowering::canCreateUndefOrPoisonForTargetNode(
Op, DemandedElts, DAG, PoisonOnly, ConsiderFlags, Depth);
}

const Constant *
RISCVTargetLowering::getTargetConstantFromLoad(LoadSDNode *Ld) const {
assert(Ld && "Unexpected null LoadSDNode");
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6 changes: 6 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.h
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Expand Up @@ -585,6 +585,12 @@ class RISCVTargetLowering : public TargetLowering {
const SelectionDAG &DAG,
unsigned Depth) const override;

bool canCreateUndefOrPoisonForTargetNode(SDValue Op,
const APInt &DemandedElts,
const SelectionDAG &DAG,
bool PoisonOnly, bool ConsiderFlags,
unsigned Depth) const override;

const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;

// This method returns the name of a target specific DAG node.
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118 changes: 54 additions & 64 deletions llvm/test/CodeGen/RISCV/double-convert.ll
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Expand Up @@ -683,47 +683,41 @@ define i64 @fcvt_l_d(double %a) nounwind {
define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32IFD-LABEL: fcvt_l_d_sat:
; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: lui a0, %hi(.LCPI12_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI12_1)
; RV32IFD-NEXT: fld fa4, %lo(.LCPI12_1)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: flt.d s0, fa5, fa0
; RV32IFD-NEXT: neg s1, s0
; RV32IFD-NEXT: fle.d s2, fa4, fa0
; RV32IFD-NEXT: neg s3, s2
; RV32IFD-NEXT: fle.d s0, fa5, fa0
; RV32IFD-NEXT: call __fixdfdi
; RV32IFD-NEXT: and a0, s3, a0
; RV32IFD-NEXT: or a0, s1, a0
; RV32IFD-NEXT: feq.d a2, fs0, fs0
; RV32IFD-NEXT: neg a2, a2
; RV32IFD-NEXT: lui a4, 524288
; RV32IFD-NEXT: li a5, 1
; RV32IFD-NEXT: lui a3, 524288
; RV32IFD-NEXT: bne s2, a5, .LBB12_2
; RV32IFD-NEXT: li a4, 1
; RV32IFD-NEXT: lui a2, 524288
; RV32IFD-NEXT: bne s0, a4, .LBB12_2
; RV32IFD-NEXT: # %bb.1: # %start
; RV32IFD-NEXT: mv a3, a1
; RV32IFD-NEXT: mv a2, a1
; RV32IFD-NEXT: .LBB12_2: # %start
; RV32IFD-NEXT: and a0, a2, a0
; RV32IFD-NEXT: beqz s0, .LBB12_4
; RV32IFD-NEXT: lui a1, %hi(.LCPI12_1)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_1)(a1)
; RV32IFD-NEXT: flt.d a4, fa5, fs0
; RV32IFD-NEXT: beqz a4, .LBB12_4
; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: addi a3, a4, -1
; RV32IFD-NEXT: addi a2, a3, -1
; RV32IFD-NEXT: .LBB12_4: # %start
; RV32IFD-NEXT: and a1, a2, a3
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: feq.d a1, fs0, fs0
; RV32IFD-NEXT: neg a3, a1
; RV32IFD-NEXT: and a1, a3, a2
; RV32IFD-NEXT: neg a2, a4
; RV32IFD-NEXT: neg a4, s0
; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a0, a3, a0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_l_d_sat:
Expand All @@ -737,48 +731,44 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fcvt_l_d_sat:
; RV32IZFINXZDINX: # %bb.0: # %start
; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a2)
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: mv s1, a1
; RV32IZFINXZDINX-NEXT: mv s0, a0
; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
; RV32IZFINXZDINX-NEXT: neg s3, s2
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_1)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_1+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_1)(a2)
; RV32IZFINXZDINX-NEXT: and a0, s3, a0
; RV32IZFINXZDINX-NEXT: flt.d a3, a2, s0
; RV32IZFINXZDINX-NEXT: neg a2, a3
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0)
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_0+4)(a2)
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a2)
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
; RV32IZFINXZDINX-NEXT: lui a5, 524288
; RV32IZFINXZDINX-NEXT: li a6, 1
; RV32IZFINXZDINX-NEXT: lui a4, 524288
; RV32IZFINXZDINX-NEXT: bne s2, a6, .LBB12_2
; RV32IZFINXZDINX-NEXT: li a4, 1
; RV32IZFINXZDINX-NEXT: lui a3, 524288
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB12_2
; RV32IZFINXZDINX-NEXT: # %bb.1: # %start
; RV32IZFINXZDINX-NEXT: mv a4, a1
; RV32IZFINXZDINX-NEXT: mv a3, a1
; RV32IZFINXZDINX-NEXT: .LBB12_2: # %start
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: beqz a3, .LBB12_4
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI12_1)
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI12_1)(a1)
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI12_1+4)(a1)
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB12_4
; RV32IZFINXZDINX-NEXT: # %bb.3:
; RV32IZFINXZDINX-NEXT: addi a4, a5, -1
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
; RV32IZFINXZDINX-NEXT: .LBB12_4: # %start
; RV32IZFINXZDINX-NEXT: and a1, a2, a4
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
; RV32IZFINXZDINX-NEXT: neg a5, a1
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
; RV32IZFINXZDINX-NEXT: neg a2, a2
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
; RV32IZFINXZDINX-NEXT: neg a2, a4
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcvt_l_d_sat:
Expand Down
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