Skip to content

[AMDGPU] Add eventMask function in WaitcntGenerator class (NFC) #85210

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Mar 15, 2024
Merged

[AMDGPU] Add eventMask function in WaitcntGenerator class (NFC) #85210

Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
b626059
[AMDGPU] Add eventMask function in WaitcntGenerator class (NFC)
cdevadas Mar 14, 2024
8b7957a
made eventMask a constexpr
cdevadas Mar 14, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
41 changes: 24 additions & 17 deletions llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -485,6 +485,16 @@ class WaitcntGenerator {
virtual AMDGPU::Waitcnt getAllZeroWaitcnt(bool IncludeVSCnt) const = 0;

virtual ~WaitcntGenerator() = default;

// Create a mask value from the initializer list of wait event types.
static constexpr unsigned
eventMask(std::initializer_list<WaitEventType> Events) {
unsigned Mask = 0;
for (auto &E : Events)
Mask |= 1 << E;

return Mask;
}
};

class WaitcntGeneratorPreGFX12 : public WaitcntGenerator {
Expand All @@ -506,14 +516,12 @@ class WaitcntGeneratorPreGFX12 : public WaitcntGenerator {
assert(ST);

static const unsigned WaitEventMaskForInstPreGFX12[NUM_INST_CNTS] = {
(1 << VMEM_ACCESS) | (1 << VMEM_READ_ACCESS) |
(1 << VMEM_SAMPLER_READ_ACCESS) | (1 << VMEM_BVH_READ_ACCESS),
(1 << SMEM_ACCESS) | (1 << LDS_ACCESS) | (1 << GDS_ACCESS) |
(1 << SQ_MESSAGE),
(1 << EXP_GPR_LOCK) | (1 << GDS_GPR_LOCK) | (1 << VMW_GPR_LOCK) |
(1 << EXP_PARAM_ACCESS) | (1 << EXP_POS_ACCESS) |
(1 << EXP_LDS_ACCESS),
(1 << VMEM_WRITE_ACCESS) | (1 << SCRATCH_WRITE_ACCESS),
eventMask({VMEM_ACCESS, VMEM_READ_ACCESS, VMEM_SAMPLER_READ_ACCESS,
VMEM_BVH_READ_ACCESS}),
eventMask({SMEM_ACCESS, LDS_ACCESS, GDS_ACCESS, SQ_MESSAGE}),
eventMask({EXP_GPR_LOCK, GDS_GPR_LOCK, VMW_GPR_LOCK, EXP_PARAM_ACCESS,
EXP_POS_ACCESS, EXP_LDS_ACCESS}),
eventMask({VMEM_WRITE_ACCESS, SCRATCH_WRITE_ACCESS}),
0,
0,
0};
Expand Down Expand Up @@ -543,15 +551,14 @@ class WaitcntGeneratorGFX12Plus : public WaitcntGenerator {
assert(ST);

static const unsigned WaitEventMaskForInstGFX12Plus[NUM_INST_CNTS] = {
(1 << VMEM_ACCESS) | (1 << VMEM_READ_ACCESS),
(1 << LDS_ACCESS) | (1 << GDS_ACCESS),
(1 << EXP_GPR_LOCK) | (1 << GDS_GPR_LOCK) | (1 << VMW_GPR_LOCK) |
(1 << EXP_PARAM_ACCESS) | (1 << EXP_POS_ACCESS) |
(1 << EXP_LDS_ACCESS),
(1 << VMEM_WRITE_ACCESS) | (1 << SCRATCH_WRITE_ACCESS),
(1 << VMEM_SAMPLER_READ_ACCESS),
(1 << VMEM_BVH_READ_ACCESS),
(1 << SMEM_ACCESS) | (1 << SQ_MESSAGE)};
eventMask({VMEM_ACCESS, VMEM_READ_ACCESS}),
eventMask({LDS_ACCESS, GDS_ACCESS}),
eventMask({EXP_GPR_LOCK, GDS_GPR_LOCK, VMW_GPR_LOCK, EXP_PARAM_ACCESS,
EXP_POS_ACCESS, EXP_LDS_ACCESS}),
eventMask({VMEM_WRITE_ACCESS, SCRATCH_WRITE_ACCESS}),
eventMask({VMEM_SAMPLER_READ_ACCESS}),
eventMask({VMEM_BVH_READ_ACCESS}),
eventMask({SMEM_ACCESS, SQ_MESSAGE})};

return WaitEventMaskForInstGFX12Plus;
}
Expand Down