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[DAGCombiner] Simplifying {si|ui}tofp when only signbit is needed #85445

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[DAGCombiner] Simplifying {si|ui}tofp when only signbit is needed #85445

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37e6b34
[DAGCombiner] Add tests for simplifying `{si|ui}tofp`; NFC
goldsteinn Mar 15, 2024
b8b3e10
[DAGCombiner] Simplifying `{si|ui}tofp` when only signbit is needed
goldsteinn Mar 15, 2024
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30 changes: 30 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -611,6 +611,25 @@ bool TargetLowering::ShrinkDemandedOp(SDValue Op, unsigned BitWidth,
return false;
}

static SDValue simplifyUseOfIntToFP(SDValue Op, const APInt &DemandedBits,
SelectionDAG &DAG) {
unsigned Opc = Op.getOpcode();
assert((Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP) &&
"Invalid Int -> FP Opcode");
if (!DemandedBits.isSignMask())
return SDValue();

EVT VT = Op.getValueType();
if (Opc == ISD::UINT_TO_FP)
return DAG.getConstant(0, SDLoc(Op), VT);

EVT InnerVT = Op.getOperand(0).getValueType();
if (VT.getScalarSizeInBits() == InnerVT.getScalarSizeInBits())
return DAG.getBitcast(VT, Op.getOperand(0));

return SDValue();
}

bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
Expand Down Expand Up @@ -816,6 +835,11 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
}
break;
}
case ISD::UINT_TO_FP:
case ISD::SINT_TO_FP:
if (SDValue R = simplifyUseOfIntToFP(Op, DemandedBits, DAG))
return R;
break;
case ISD::SIGN_EXTEND_INREG: {
// If none of the extended bits are demanded, eliminate the sextinreg.
SDValue Op0 = Op.getOperand(0);
Expand Down Expand Up @@ -2313,6 +2337,12 @@ bool TargetLowering::SimplifyDemandedBits(
Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
break;
}
case ISD::UINT_TO_FP:
case ISD::SINT_TO_FP:
if (SDValue R = simplifyUseOfIntToFP(Op, DemandedBits, TLO.DAG))
return TLO.CombineTo(Op, R);
Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
break;
case ISD::SIGN_EXTEND_INREG: {
SDValue Op0 = Op.getOperand(0);
EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/X86/combine-sse41-intrinsics.ll
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Expand Up @@ -164,14 +164,13 @@ define <4 x float> @demandedbits_sitofp_blendvps(<4 x float> %a0, <4 x float> %a
; SSE-LABEL: demandedbits_sitofp_blendvps:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm3
; SSE-NEXT: cvtdq2ps %xmm2, %xmm0
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: blendvps %xmm0, %xmm1, %xmm3
; SSE-NEXT: movaps %xmm3, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: demandedbits_sitofp_blendvps:
; AVX: # %bb.0:
; AVX-NEXT: vcvtdq2ps %xmm2, %xmm2
; AVX-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%cvt = sitofp <4 x i32> %a2 to <4 x float>
Expand Down
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