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[RISCV][GISEL] Legalization, register bank selection, and instruction selection for scalable G_SELECT #85540

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[RISCV][GISEL] Legalization, register bank selection, and instruction selection for scalable G_SELECT #85540

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c97a262
[RISCV][GISEL][WIP] Legalize G_SELECT for scalable vectors
michaelmaitland Mar 15, 2024
3728844
[RISCV][GISEL] Regbank select for scalable G_SELECT
michaelmaitland Mar 15, 2024
321be4f
[RISCV][GISEL] Instruction select for scalable G_SELECT
michaelmaitland Mar 15, 2024
0ba9147
fixup! use GSelect
michaelmaitland Mar 18, 2024
6b2ff9d
fixup! add assert
michaelmaitland Mar 19, 2024
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1 change: 1 addition & 0 deletions llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
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Expand Up @@ -90,6 +90,7 @@ def : GINodeEquiv<G_UDIVFIX, udivfix>;
def : GINodeEquiv<G_SDIVFIXSAT, sdivfixsat>;
def : GINodeEquiv<G_UDIVFIXSAT, udivfixsat>;
def : GINodeEquiv<G_SELECT, select>;
def : GINodeEquiv<G_SELECT, vselect>;
def : GINodeEquiv<G_FNEG, fneg>;
def : GINodeEquiv<G_FPEXT, fpextend>;
def : GINodeEquiv<G_FPTRUNC, fpround>;
Expand Down
7 changes: 5 additions & 2 deletions llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Expand Up @@ -202,8 +202,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.clampScalar(1, sXLen, sXLen)
.clampScalar(0, sXLen, sXLen);

auto &SelectActions = getActionDefinitionsBuilder(G_SELECT).legalFor(
{{s32, sXLen}, {p0, sXLen}});
auto &SelectActions =
getActionDefinitionsBuilder(G_SELECT)
.legalFor({{s32, sXLen}, {p0, sXLen}})
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non-0 address space pointers?

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Can we do that in a different patch? I am taking the existing legalFor from scalar and only adding for vectors. I specific in the PR title that this is just for scalable G_SELECT.

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Yes, just pointing out this isn't free anymore

.legalIf(all(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
typeIsLegalBoolVec(1, BoolVecTys, ST)));
if (XLen == 64 || ST.hasStdExtD())
SelectActions.legalFor({{s64, sXLen}});
SelectActions.widenScalarToNextPow2(0)
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12 changes: 12 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
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Expand Up @@ -13,6 +13,7 @@
#include "RISCVRegisterBankInfo.h"
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterBank.h"
#include "llvm/CodeGen/RegisterBankInfo.h"
Expand Down Expand Up @@ -401,6 +402,17 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_SELECT: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());

if (Ty.isVector()) {
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You could try

 GSelect *Sel = cast<GSelect>(&MI);

, but ...

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Are you suggesting: MI.getOperand(2).getReg() -> GSelect *Sel = cast<GSelect>(&MI); MRI.getType(Sel->getCondReg())?

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Exactly. Then you don't have to remember the operand indices and the code becomes more readable.

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Updated

GSelect *Sel = cast<GSelect>(&MI);
LLT TestTy = MRI.getType(Sel->getCondReg());
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assert that TestTy is vector

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Updated

assert(TestTy.isVector() && "Unexpected condition argument type");
OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] =
getVRBValueMapping(Ty.getSizeInBits().getKnownMinValue());
OpdsMapping[1] =
getVRBValueMapping(TestTy.getSizeInBits().getKnownMinValue());
break;
}

// Try to minimize the number of copies. If we have more floating point
// constrained values than not, then we'll put everything on FPR. Otherwise,
// everything has to be on GPR.
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345 changes: 345 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir
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@@ -0,0 +1,345 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s

---
name: select_nxv1i8
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; RV32I-LABEL: name: select_nxv1i8
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
; RV32I-NEXT: $v0 = COPY [[DEF]]
; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */
; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]
; RV32I-NEXT: PseudoRET implicit $v8
;
; RV64I-LABEL: name: select_nxv1i8
; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
; RV64I-NEXT: $v0 = COPY [[DEF]]
; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */
; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]
; RV64I-NEXT: PseudoRET implicit $v8
%0:vrb(<vscale x 2 x s1>) = G_IMPLICIT_DEF
%1:vrb(<vscale x 2 x s8>) = G_IMPLICIT_DEF
%2:vrb(<vscale x 2 x s8>) = G_SELECT %0(<vscale x 2 x s1>), %1, %1
$v8 = COPY %2(<vscale x 2 x s8>)
PseudoRET implicit $v8

...
---
name: select_nxv4i8
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; RV32I-LABEL: name: select_nxv4i8
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
; RV32I-NEXT: $v0 = COPY [[DEF]]
; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */
; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]
; RV32I-NEXT: PseudoRET implicit $v8
;
; RV64I-LABEL: name: select_nxv4i8
; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
; RV64I-NEXT: $v0 = COPY [[DEF]]
; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */
; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]
; RV64I-NEXT: PseudoRET implicit $v8
%0:vrb(<vscale x 8 x s1>) = G_IMPLICIT_DEF
%1:vrb(<vscale x 8 x s8>) = G_IMPLICIT_DEF
%2:vrb(<vscale x 8 x s8>) = G_SELECT %0(<vscale x 8 x s1>), %1, %1
$v8 = COPY %2(<vscale x 8 x s8>)
PseudoRET implicit $v8

...
---
name: select_nxv16i8
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; RV32I-LABEL: name: select_nxv16i8
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
; RV32I-NEXT: $v0 = COPY [[DEF]]
; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */
; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]
; RV32I-NEXT: PseudoRET implicit $v8m4
;
; RV64I-LABEL: name: select_nxv16i8
; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
; RV64I-NEXT: $v0 = COPY [[DEF]]
; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */
; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]
; RV64I-NEXT: PseudoRET implicit $v8m4
%0:vrb(<vscale x 32 x s1>) = G_IMPLICIT_DEF
%1:vrb(<vscale x 32 x s8>) = G_IMPLICIT_DEF
%2:vrb(<vscale x 32 x s8>) = G_SELECT %0(<vscale x 32 x s1>), %1, %1
$v8m4 = COPY %2(<vscale x 32 x s8>)
PseudoRET implicit $v8m4

...
---
name: select_nxv64i8
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; RV32I-LABEL: name: select_nxv64i8
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
; RV32I-NEXT: $v0 = COPY [[DEF]]
; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */
; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]
; RV32I-NEXT: PseudoRET implicit $v8
;
; RV64I-LABEL: name: select_nxv64i8
; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
; RV64I-NEXT: $v0 = COPY [[DEF]]
; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */
; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]
; RV64I-NEXT: PseudoRET implicit $v8
%0:vrb(<vscale x 1 x s1>) = G_IMPLICIT_DEF
%1:vrb(<vscale x 1 x s16>) = G_IMPLICIT_DEF
%2:vrb(<vscale x 1 x s16>) = G_SELECT %0(<vscale x 1 x s1>), %1, %1
$v8 = COPY %2(<vscale x 1 x s16>)
PseudoRET implicit $v8

...
---
name: select_nxv2i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; RV32I-LABEL: name: select_nxv2i16
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
; RV32I-NEXT: $v0 = COPY [[DEF]]
; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */
; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]
; RV32I-NEXT: PseudoRET implicit $v8
;
; RV64I-LABEL: name: select_nxv2i16
; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
; RV64I-NEXT: $v0 = COPY [[DEF]]
; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */
; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]
; RV64I-NEXT: PseudoRET implicit $v8
%0:vrb(<vscale x 4 x s1>) = G_IMPLICIT_DEF
%1:vrb(<vscale x 4 x s16>) = G_IMPLICIT_DEF
%2:vrb(<vscale x 4 x s16>) = G_SELECT %0(<vscale x 4 x s1>), %1, %1
$v8 = COPY %2(<vscale x 4 x s16>)
PseudoRET implicit $v8

...
---
name: select_nxv8i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; RV32I-LABEL: name: select_nxv8i16
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
; RV32I-NEXT: $v0 = COPY [[DEF]]
; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */
; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]
; RV32I-NEXT: PseudoRET implicit $v8m4
;
; RV64I-LABEL: name: select_nxv8i16
; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
; RV64I-NEXT: $v0 = COPY [[DEF]]
; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */
; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]
; RV64I-NEXT: PseudoRET implicit $v8m4
%0:vrb(<vscale x 16 x s1>) = G_IMPLICIT_DEF
%1:vrb(<vscale x 16 x s16>) = G_IMPLICIT_DEF
%2:vrb(<vscale x 16 x s16>) = G_SELECT %0(<vscale x 16 x s1>), %1, %1
$v8m4 = COPY %2(<vscale x 16 x s16>)
PseudoRET implicit $v8m4

...
---
name: select_nxv32i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; RV32I-LABEL: name: select_nxv32i16
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
; RV32I-NEXT: $v0 = COPY [[DEF]]
; RV32I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */
; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]]
; RV32I-NEXT: PseudoRET implicit $v8
;
; RV64I-LABEL: name: select_nxv32i16
; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
; RV64I-NEXT: $v0 = COPY [[DEF]]
; RV64I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */
; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]]
; RV64I-NEXT: PseudoRET implicit $v8
%0:vrb(<vscale x 1 x s1>) = G_IMPLICIT_DEF
%1:vrb(<vscale x 1 x s32>) = G_IMPLICIT_DEF
%2:vrb(<vscale x 1 x s32>) = G_SELECT %0(<vscale x 1 x s1>), %1, %1
$v8 = COPY %2(<vscale x 1 x s32>)
PseudoRET implicit $v8

...
---
name: select_nxv2i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; RV32I-LABEL: name: select_nxv2i32
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
; RV32I-NEXT: $v0 = COPY [[DEF]]
; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */
; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]
; RV32I-NEXT: PseudoRET implicit $v8m2
;
; RV64I-LABEL: name: select_nxv2i32
; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
; RV64I-NEXT: $v0 = COPY [[DEF]]
; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */
; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]
; RV64I-NEXT: PseudoRET implicit $v8m2
%0:vrb(<vscale x 4 x s1>) = G_IMPLICIT_DEF
%1:vrb(<vscale x 4 x s32>) = G_IMPLICIT_DEF
%2:vrb(<vscale x 4 x s32>) = G_SELECT %0(<vscale x 4 x s1>), %1, %1
$v8m2 = COPY %2(<vscale x 4 x s32>)
PseudoRET implicit $v8m2

...
---
name: select_nxv8i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; RV32I-LABEL: name: select_nxv8i32
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
; RV32I-NEXT: $v0 = COPY [[DEF]]
; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */
; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]
; RV32I-NEXT: PseudoRET implicit $v8m8
;
; RV64I-LABEL: name: select_nxv8i32
; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
; RV64I-NEXT: $v0 = COPY [[DEF]]
; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */
; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]
; RV64I-NEXT: PseudoRET implicit $v8m8
%0:vrb(<vscale x 16 x s1>) = G_IMPLICIT_DEF
%1:vrb(<vscale x 16 x s32>) = G_IMPLICIT_DEF
%2:vrb(<vscale x 16 x s32>) = G_SELECT %0(<vscale x 16 x s1>), %1, %1
$v8m8 = COPY %2(<vscale x 16 x s32>)
PseudoRET implicit $v8m8

...
---
name: select_nxv1i64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; RV32I-LABEL: name: select_nxv1i64
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
; RV32I-NEXT: $v0 = COPY [[DEF]]
; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 6 /* e64 */
; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]
; RV32I-NEXT: PseudoRET implicit $v8m2
;
; RV64I-LABEL: name: select_nxv1i64
; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
; RV64I-NEXT: $v0 = COPY [[DEF]]
; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 6 /* e64 */
; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]
; RV64I-NEXT: PseudoRET implicit $v8m2
%0:vrb(<vscale x 2 x s1>) = G_IMPLICIT_DEF
%1:vrb(<vscale x 2 x s64>) = G_IMPLICIT_DEF
%2:vrb(<vscale x 2 x s64>) = G_SELECT %0(<vscale x 2 x s1>), %1, %1
$v8m2 = COPY %2(<vscale x 2 x s64>)
PseudoRET implicit $v8m2

...
---
name: select_nxv4i64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
; RV32I-LABEL: name: select_nxv4i64
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
; RV32I-NEXT: $v0 = COPY [[DEF]]
; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 6 /* e64 */
; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]
; RV32I-NEXT: PseudoRET implicit $v8m8
;
; RV64I-LABEL: name: select_nxv4i64
; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
; RV64I-NEXT: $v0 = COPY [[DEF]]
; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 6 /* e64 */
; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]
; RV64I-NEXT: PseudoRET implicit $v8m8
%0:vrb(<vscale x 8 x s1>) = G_IMPLICIT_DEF
%1:vrb(<vscale x 8 x s64>) = G_IMPLICIT_DEF
%2:vrb(<vscale x 8 x s64>) = G_SELECT %0(<vscale x 8 x s1>), %1, %1
$v8m8 = COPY %2(<vscale x 8 x s64>)
PseudoRET implicit $v8m8

...
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