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[RISCV] Implement Intrinsics Support for XCValu Extension in CV32E40P #85603

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Merged
merged 1 commit into from
Jul 3, 2024
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[RISCV] Implement Intrinsics Support for XCValu Extension in CV32E40P #85603

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23 changes: 23 additions & 0 deletions llvm/include/llvm/IR/IntrinsicsRISCVXCV.td
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,18 @@ class ScalarCoreVBitManipGprIntrinsic
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
[IntrNoMem, IntrSpeculatable]>;

class ScalarCoreVAluGprIntrinsic
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
[IntrNoMem, IntrSpeculatable]>;

class ScalarCoreVAluGprGprIntrinsic
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, IntrSpeculatable]>;

class ScalarCoreVAluGprGprGprIntrinsic
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, IntrSpeculatable]>;

let TargetPrefix = "riscv" in {
def int_riscv_cv_bitmanip_extract : ScalarCoreVBitManipGprGprIntrinsic;
def int_riscv_cv_bitmanip_extractu : ScalarCoreVBitManipGprGprIntrinsic;
Expand All @@ -34,4 +46,15 @@ let TargetPrefix = "riscv" in {
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, IntrWillReturn, IntrSpeculatable,
ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;

def int_riscv_cv_alu_clip : ScalarCoreVAluGprGprIntrinsic;
def int_riscv_cv_alu_clipu : ScalarCoreVAluGprGprIntrinsic;
def int_riscv_cv_alu_addn : ScalarCoreVAluGprGprGprIntrinsic;
def int_riscv_cv_alu_addun : ScalarCoreVAluGprGprGprIntrinsic;
def int_riscv_cv_alu_addrn : ScalarCoreVAluGprGprGprIntrinsic;
def int_riscv_cv_alu_addurn : ScalarCoreVAluGprGprGprIntrinsic;
def int_riscv_cv_alu_subn : ScalarCoreVAluGprGprGprIntrinsic;
def int_riscv_cv_alu_subun : ScalarCoreVAluGprGprGprIntrinsic;
def int_riscv_cv_alu_subrn : ScalarCoreVAluGprGprGprIntrinsic;
def int_riscv_cv_alu_suburn : ScalarCoreVAluGprGprGprIntrinsic;
} // TargetPrefix = "riscv"
16 changes: 14 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -250,10 +250,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (RV64LegalI32 && Subtarget.is64Bit())
setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);

setCondCodeAction(ISD::SETLE, XLenVT, Expand);
if (!Subtarget.hasVendorXCValu())
setCondCodeAction(ISD::SETLE, XLenVT, Expand);
setCondCodeAction(ISD::SETGT, XLenVT, Custom);
setCondCodeAction(ISD::SETGE, XLenVT, Expand);
setCondCodeAction(ISD::SETULE, XLenVT, Expand);
if (!Subtarget.hasVendorXCValu())
setCondCodeAction(ISD::SETULE, XLenVT, Expand);
setCondCodeAction(ISD::SETUGT, XLenVT, Custom);
setCondCodeAction(ISD::SETUGE, XLenVT, Expand);

Expand Down Expand Up @@ -1453,6 +1455,16 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
}

if (Subtarget.hasVendorXCValu()) {
setOperationAction(ISD::ABS, XLenVT, Legal);
setOperationAction(ISD::SMIN, XLenVT, Legal);
setOperationAction(ISD::UMIN, XLenVT, Legal);
setOperationAction(ISD::SMAX, XLenVT, Legal);
setOperationAction(ISD::UMAX, XLenVT, Legal);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
}

// Function alignments.
const Align FunctionAlignment(Subtarget.hasStdExtCOrZca() ? 2 : 4);
setMinFunctionAlignment(FunctionAlignment);
Expand Down
63 changes: 58 additions & 5 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
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Original file line number Diff line number Diff line change
Expand Up @@ -198,7 +198,7 @@ let DecoderNamespace = "XCValu" in {

} // DecoderNamespace = "XCValu"

let Predicates = [HasVendorXCValu],
let Predicates = [HasVendorXCValu, IsRV32],
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
// General ALU Operations
def CV_ABS : CVInstAluR<0b0101000, 0b011, "cv.abs">,
Expand Down Expand Up @@ -249,10 +249,10 @@ let Predicates = [HasVendorXCValu],
Sched<[]>;
def CV_SUBURN : CVInstAluRRI<0b11, 0b011, "cv.suburn">,
Sched<[]>;
} // Predicates = [HasVendorXCValu],
} // Predicates = [HasVendorXCValu, IsRV32],
// hasSideEffects = 0, mayLoad = 0, mayStore = 0

let Predicates = [HasVendorXCValu],
let Predicates = [HasVendorXCValu, IsRV32],
hasSideEffects = 0, mayLoad = 0, mayStore = 0,
Constraints = "$rd = $rd_wb" in {
def CV_ADDNR : CVInstAluRRNR<0b1000000, 0b011, "cv.addnr">,
Expand All @@ -272,7 +272,7 @@ let Predicates = [HasVendorXCValu],
def CV_SUBURNR : CVInstAluRRNR<0b1000111, 0b011, "cv.suburnr">,
Sched<[]>;

} // Predicates = [HasVendorXCValu],
} // Predicates = [HasVendorXCValu, IsRV32],
// hasSideEffects = 0, mayLoad = 0, mayStore = 0,
// Constraints = "$rd = $rd_wb"

Expand Down Expand Up @@ -716,6 +716,13 @@ def CV_HI5: SDNodeXForm<imm, [{
N->getValueType(0));
}]>;

def powerOf2Minus1 : ImmLeaf<XLenVT, [{ return isPowerOf2_32(Imm+1); }]>;
def trailing1sPlus1 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(
llvm::countr_one(N->getZExtValue()) + 1,
SDLoc(N), N->getValueType(0));
}]>;

multiclass PatCoreVBitManip<Intrinsic intr> {
def : PatGprGpr<intr, !cast<RVInst>("CV_" # NAME # "R")>;
def : Pat<(intr GPR:$rs1, cv_uimm10:$imm),
Expand Down Expand Up @@ -748,8 +755,54 @@ let Predicates = [HasVendorXCVbitmanip, IsRV32] in {
def : Pat<(bitreverse (XLenVT GPR:$rs)), (CV_BITREV GPR:$rs, 0, 0)>;
}

class PatCoreVAluGpr<string intr, string asm> :
PatGpr<!cast<Intrinsic>("int_riscv_cv_alu_" # intr),
!cast<RVInst>("CV_" # asm)>;
class PatCoreVAluGprGpr <string intr, string asm> :
PatGprGpr<!cast<Intrinsic>("int_riscv_cv_alu_" # intr),
!cast<RVInst>("CV_" # asm)>;

multiclass PatCoreVAluGprImm<Intrinsic intr> {
def : PatGprGpr<intr, !cast<RVInst>("CV_" # NAME # "R")>;
def : Pat<(intr (XLenVT GPR:$rs1), powerOf2Minus1:$upperBound),
(!cast<RVInst>("CV_" # NAME) GPR:$rs1,
(trailing1sPlus1 imm:$upperBound))>;
}

multiclass PatCoreVAluGprGprImm<Intrinsic intr> {
def : Pat<(intr GPR:$rs1, GPR:$rs2, GPR:$rs3),
(!cast<RVInst>("CV_" # NAME # "R") GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(intr GPR:$rs1, GPR:$rs2, uimm5:$imm),
(!cast<RVInst>("CV_" # NAME) GPR:$rs1, GPR:$rs2, uimm5:$imm)>;
}

let Predicates = [HasVendorXCValu, IsRV32], AddedComplexity = 1 in {
def : PatGpr<abs, CV_ABS>;
def : PatGprGpr<setle, CV_SLET>;
def : PatGprGpr<setule, CV_SLETU>;
def : PatGprGpr<smin, CV_MIN>;
def : PatGprGpr<umin, CV_MINU>;
def : PatGprGpr<smax, CV_MAX>;
def : PatGprGpr<umax, CV_MAXU>;

def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (CV_EXTHS GPR:$rs1)>;
def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (CV_EXTBS GPR:$rs1)>;
def : Pat<(and (XLenVT GPR:$rs1), 0xffff), (CV_EXTHZ GPR:$rs1)>;

defm CLIP : PatCoreVAluGprImm<int_riscv_cv_alu_clip>;
defm CLIPU : PatCoreVAluGprImm<int_riscv_cv_alu_clipu>;
defm ADDN : PatCoreVAluGprGprImm<int_riscv_cv_alu_addn>;
defm ADDUN : PatCoreVAluGprGprImm<int_riscv_cv_alu_addun>;
defm ADDRN : PatCoreVAluGprGprImm<int_riscv_cv_alu_addrn>;
defm ADDURN : PatCoreVAluGprGprImm<int_riscv_cv_alu_addurn>;
defm SUBN : PatCoreVAluGprGprImm<int_riscv_cv_alu_subn>;
defm SUBUN : PatCoreVAluGprGprImm<int_riscv_cv_alu_subun>;
defm SUBRN : PatCoreVAluGprGprImm<int_riscv_cv_alu_subrn>;
defm SUBURN : PatCoreVAluGprGprImm<int_riscv_cv_alu_suburn>;
} // Predicates = [HasVendorXCValu, IsRV32]

//===----------------------------------------------------------------------===//
// Patterns for immediate branching operations
// Patterns for immediate branching operations
//===----------------------------------------------------------------------===//

let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
Expand Down
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