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[MLIR][SROA][Mem2Reg] Add data layout to interface methods #85644
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Doesn't this remain true in the context of the
PromotableMemOpInterface
used by the Mem2Reg pass?There was a problem hiding this comment.
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It's not yet fully clear if this requirement will remain valid for LLVM dialect. I can remove this change and adapt it when it shows to no longer hold.
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After some more though, this is really no longer needed. Changing the LLVM load and store interface implementations to support loading an smaller type from a larger slot should be easy enough.
We are in fact considering such changes, as the type consistency pass showed to produce substantial performance degradations for parts of our benchmark set.
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What about loading larger types from smaller slots?
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This is not supported, as this would break things on multiple levels. See the stacked PR for the constrains added specifically in SROA. The additional steps for Mem2Reg will be added in subsequent patches.
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I don’t understand, I would say it is obviously not supported, hence why the original documentation was there. I’m not sure where else the constraints on bounding are documented if you remove this.
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I can clarify in the comment that only in-bounds accesses should be considered valid.