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[X86] Support DomainReassignment for APX NDD instructions #85737

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Merged
merged 4 commits into from
Mar 22, 2024
Merged

[X86] Support DomainReassignment for APX NDD instructions #85737

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fe69f1c
[X86][DomainReassignment] Support APX NDD instructions.
FreddyLeaf Mar 19, 2024
1b56ea2
Merge branch 'main' into ndd_domain_reass
FreddyLeaf Mar 21, 2024
3cc5b2e
Apply changes to pre-commit test instead.
FreddyLeaf Mar 21, 2024
4c9f3b6
Merge branch 'main' into ndd_domain_reass
FreddyLeaf Mar 21, 2024
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38 changes: 38 additions & 0 deletions llvm/lib/Target/X86/X86DomainReassignment.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -650,6 +650,16 @@ void X86DomainReassignment::initConverters() {
createReplacer(X86::AND16rr, X86::KANDWrr);
createReplacer(X86::XOR16rr, X86::KXORWrr);

bool HasNDD = STI->hasNDD();
if (HasNDD) {
createReplacer(X86::SHR16ri_ND, X86::KSHIFTRWri);
createReplacer(X86::SHL16ri_ND, X86::KSHIFTLWri);
createReplacer(X86::NOT16r_ND, X86::KNOTWrr);
createReplacer(X86::OR16rr_ND, X86::KORWrr);
createReplacer(X86::AND16rr_ND, X86::KANDWrr);
createReplacer(X86::XOR16rr_ND, X86::KXORWrr);
}

if (STI->hasBWI()) {
createReplacer(X86::MOV32rm, GET_EGPR_IF_ENABLED(X86::KMOVDkm));
createReplacer(X86::MOV64rm, GET_EGPR_IF_ENABLED(X86::KMOVQkm));
Expand Down Expand Up @@ -684,6 +694,23 @@ void X86DomainReassignment::initConverters() {
createReplacer(X86::XOR32rr, X86::KXORDrr);
createReplacer(X86::XOR64rr, X86::KXORQrr);

if (HasNDD) {
createReplacer(X86::SHR32ri_ND, X86::KSHIFTRDri);
createReplacer(X86::SHL32ri_ND, X86::KSHIFTLDri);
createReplacer(X86::ADD32rr_ND, X86::KADDDrr);
createReplacer(X86::NOT32r_ND, X86::KNOTDrr);
createReplacer(X86::OR32rr_ND, X86::KORDrr);
createReplacer(X86::AND32rr_ND, X86::KANDDrr);
createReplacer(X86::XOR32rr_ND, X86::KXORDrr);
createReplacer(X86::SHR64ri_ND, X86::KSHIFTRQri);
createReplacer(X86::SHL64ri_ND, X86::KSHIFTLQri);
createReplacer(X86::ADD64rr_ND, X86::KADDQrr);
createReplacer(X86::NOT64r_ND, X86::KNOTQrr);
createReplacer(X86::OR64rr_ND, X86::KORQrr);
createReplacer(X86::AND64rr_ND, X86::KANDQrr);
createReplacer(X86::XOR64rr_ND, X86::KXORQrr);
}

// TODO: KTEST is not a replacement for TEST due to flag differences. Need
// to prove only Z flag is used.
// createReplacer(X86::TEST32rr, X86::KTESTDrr);
Expand Down Expand Up @@ -713,6 +740,17 @@ void X86DomainReassignment::initConverters() {
// createReplacer(X86::TEST16rr, X86::KTESTWrr);

createReplacer(X86::XOR8rr, X86::KXORBrr);

if (HasNDD) {
createReplacer(X86::ADD8rr_ND, X86::KADDBrr);
createReplacer(X86::ADD16rr_ND, X86::KADDWrr);
createReplacer(X86::AND8rr_ND, X86::KANDBrr);
createReplacer(X86::NOT8r_ND, X86::KNOTBrr);
createReplacer(X86::OR8rr_ND, X86::KORBrr);
createReplacer(X86::SHR8ri_ND, X86::KSHIFTRBri);
createReplacer(X86::SHL8ri_ND, X86::KSHIFTLBri);
createReplacer(X86::XOR8rr_ND, X86::KXORBrr);
}
}
#undef GET_EGPR_IF_ENABLED
}
Expand Down
62 changes: 31 additions & 31 deletions llvm/test/CodeGen/X86/apx/domain-reassignment.mir
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass x86-domain-reassignment -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq -o - %s | FileCheck %s
# RUN: llc -run-pass x86-domain-reassignment -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq,+ndd -o - %s | FileCheck %s
--- |
; ModuleID = '../test/CodeGen/X86/gpr-to-mask.ll'
source_filename = "../test/CodeGen/X86/gpr-to-mask.ll"
Expand Down Expand Up @@ -302,13 +302,13 @@ body: |
%6 = COPY %5
%7 = COPY %6.sub_8bit

%12 = SHR8ri %7, 2, implicit-def dead $eflags
%13 = SHL8ri %12, 1, implicit-def dead $eflags
%14 = NOT8r %13
%15 = OR8rr %14, %12, implicit-def dead $eflags
%16 = AND8rr %15, %13, implicit-def dead $eflags
%17 = XOR8rr %16, %12, implicit-def dead $eflags
%18 = ADD8rr %17, %14, implicit-def dead $eflags
%12 = SHR8ri_ND %7, 2, implicit-def dead $eflags
%13 = SHL8ri_ND %12, 1, implicit-def dead $eflags
%14 = NOT8r_ND %13
%15 = OR8rr_ND %14, %12, implicit-def dead $eflags
%16 = AND8rr_ND %15, %13, implicit-def dead $eflags
%17 = XOR8rr_ND %16, %12, implicit-def dead $eflags
%18 = ADD8rr_ND %17, %14, implicit-def dead $eflags

%8 = IMPLICIT_DEF
%9 = INSERT_SUBREG %8, %18, %subreg.sub_8bit_hi
Expand Down Expand Up @@ -421,12 +421,12 @@ body: |
%6 = COPY %5
%7 = COPY %6.sub_16bit

%12 = SHR16ri %7, 2, implicit-def dead $eflags
%13 = SHL16ri %12, 1, implicit-def dead $eflags
%14 = NOT16r %13
%15 = OR16rr %14, %12, implicit-def dead $eflags
%16 = AND16rr %15, %13, implicit-def dead $eflags
%17 = XOR16rr %16, %12, implicit-def dead $eflags
%12 = SHR16ri_ND %7, 2, implicit-def dead $eflags
%13 = SHL16ri_ND %12, 1, implicit-def dead $eflags
%14 = NOT16r_ND %13
%15 = OR16rr_ND %14, %12, implicit-def dead $eflags
%16 = AND16rr_ND %15, %13, implicit-def dead $eflags
%17 = XOR16rr_ND %16, %12, implicit-def dead $eflags

%8 = IMPLICIT_DEF
%9 = INSERT_SUBREG %8, %17, %subreg.sub_16bit
Expand Down Expand Up @@ -524,14 +524,14 @@ body: |
%2 = COPY $zmm1

%5 = MOV32rm %0, 1, $noreg, 0, $noreg
%6 = SHR32ri %5, 2, implicit-def dead $eflags
%7 = SHL32ri %6, 1, implicit-def dead $eflags
%8 = NOT32r %7
%9 = OR32rr %8, %6, implicit-def dead $eflags
%10 = AND32rr %9, %7, implicit-def dead $eflags
%11 = XOR32rr %10, %6, implicit-def dead $eflags
%6 = SHR32ri_ND %5, 2, implicit-def dead $eflags
%7 = SHL32ri_ND %6, 1, implicit-def dead $eflags
%8 = NOT32r_ND %7
%9 = OR32rr_ND %8, %6, implicit-def dead $eflags
%10 = AND32rr_ND %9, %7, implicit-def dead $eflags
%11 = XOR32rr_ND %10, %6, implicit-def dead $eflags
%12 = ANDN32rr %11, %9, implicit-def dead $eflags
%13 = ADD32rr %12, %11, implicit-def dead $eflags
%13 = ADD32rr_ND %12, %11, implicit-def dead $eflags

%3 = COPY %13
%4 = VMOVDQU16Zrrk %2, killed %3, %1
Expand Down Expand Up @@ -627,14 +627,14 @@ body: |
%2 = COPY $zmm1

%5 = MOV64rm %0, 1, $noreg, 0, $noreg
%6 = SHR64ri %5, 2, implicit-def dead $eflags
%7 = SHL64ri %6, 1, implicit-def dead $eflags
%8 = NOT64r %7
%9 = OR64rr %8, %6, implicit-def dead $eflags
%10 = AND64rr %9, %7, implicit-def dead $eflags
%11 = XOR64rr %10, %6, implicit-def dead $eflags
%6 = SHR64ri_ND %5, 2, implicit-def dead $eflags
%7 = SHL64ri_ND %6, 1, implicit-def dead $eflags
%8 = NOT64r_ND %7
%9 = OR64rr_ND %8, %6, implicit-def dead $eflags
%10 = AND64rr_ND %9, %7, implicit-def dead $eflags
%11 = XOR64rr_ND %10, %6, implicit-def dead $eflags
%12 = ANDN64rr %11, %9, implicit-def dead $eflags
%13 = ADD64rr %12, %11, implicit-def dead $eflags
%13 = ADD64rr_ND %12, %11, implicit-def dead $eflags

%3 = COPY %13
%4 = VMOVDQU8Zrrk %2, killed %3, %1
Expand Down Expand Up @@ -712,7 +712,7 @@ body: |
%2 = COPY $zmm1

%5 = MOVZX16rm8 %0, 1, $noreg, 0, $noreg
%6 = NOT16r %5
%6 = NOT16r_ND %5

%3 = COPY %6
%4 = VMOVAPSZrrk %2, killed %3, %1
Expand Down Expand Up @@ -785,7 +785,7 @@ body: |

%5 = MOVZX32rm8 %0, 1, $noreg, 0, $noreg
%6 = MOVZX32rm16 %0, 1, $noreg, 0, $noreg
%7 = ADD32rr %5, %6, implicit-def dead $eflags
%7 = ADD32rr_ND %5, %6, implicit-def dead $eflags

%3 = COPY %7
%4 = VMOVDQU16Zrrk %2, killed %3, %1
Expand Down Expand Up @@ -858,7 +858,7 @@ body: |

%5 = MOVZX64rm8 %0, 1, $noreg, 0, $noreg
%6 = MOVZX64rm16 %0, 1, $noreg, 0, $noreg
%7 = ADD64rr %5, %6, implicit-def dead $eflags
%7 = ADD64rr_ND %5, %6, implicit-def dead $eflags

%3 = COPY %7
%4 = VMOVDQU8Zrrk %2, killed %3, %1
Expand Down