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[InstCombine] Clear sign-bit of the constant magnitude in copysign #85787

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Mar 19, 2024
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10 changes: 10 additions & 0 deletions llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2473,6 +2473,16 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
if (match(Sign, m_Intrinsic<Intrinsic::copysign>(m_Value(), m_Value(X))))
return replaceOperand(*II, 1, X);

// Clear sign-bit of constant magnitude:
// copysign -MagC, X --> copysign MagC, X
// TODO: Support constant folding for fabs
const APFloat *MagC;
if (match(Mag, m_APFloat(MagC)) && MagC->isNegative()) {
APFloat PosMagC = *MagC;
PosMagC.clearSign();
return replaceOperand(*II, 0, ConstantFP::get(Mag->getType(), PosMagC));
}

// Peek through changes of magnitude's sign-bit. This call rewrites those:
// copysign (fabs X), Sign --> copysign X, Sign
// copysign (fneg X), Sign --> copysign X, Sign
Expand Down
79 changes: 79 additions & 0 deletions llvm/test/Transforms/InstCombine/copysign-fneg-fabs.ll
Original file line number Diff line number Diff line change
Expand Up @@ -275,6 +275,85 @@ define half @fneg_fabs_copysign_multi_use_fabs(half %x, half %y, ptr %ptr) {
ret half %fabs.copysign
}

define half @copysign_pos(half %a) {
; CHECK-LABEL: @copysign_pos(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half 0xH3C00, half [[A:%.*]])
; CHECK-NEXT: ret half [[RET]]
;
entry:
%ret = call half @llvm.copysign.f16(half 0xH3C00, half %a)
ret half %ret
}

define half @copysign_neg(half %a) {
; CHECK-LABEL: @copysign_neg(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half 0xH3C00, half [[A:%.*]])
; CHECK-NEXT: ret half [[RET]]
;
entry:
%ret = call half @llvm.copysign.f16(half 0xHBC00, half %a)
ret half %ret
}

define half @copysign_negzero(half %a) {
; CHECK-LABEL: @copysign_negzero(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half 0xH0000, half [[A:%.*]])
; CHECK-NEXT: ret half [[RET]]
;
entry:
%ret = call half @llvm.copysign.f16(half 0xH8000, half %a)
ret half %ret
}

define half @copysign_negnan(half %a) {
; CHECK-LABEL: @copysign_negnan(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half 0xH7E00, half [[A:%.*]])
; CHECK-NEXT: ret half [[RET]]
;
entry:
%ret = call half @llvm.copysign.f16(half 0xHFE00, half %a)
ret half %ret
}

define half @copysign_neginf(half %a) {
; CHECK-LABEL: @copysign_neginf(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[RET:%.*]] = call half @llvm.copysign.f16(half 0xH7C00, half [[A:%.*]])
; CHECK-NEXT: ret half [[RET]]
;
entry:
%ret = call half @llvm.copysign.f16(half 0xHFC00, half %a)
ret half %ret
}

define <4 x half> @copysign_splat(<4 x half> %a) {
; CHECK-LABEL: @copysign_splat(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[RET:%.*]] = call <4 x half> @llvm.copysign.v4f16(<4 x half> <half 0xH3C00, half 0xH3C00, half 0xH3C00, half 0xH3C00>, <4 x half> [[A:%.*]])
; CHECK-NEXT: ret <4 x half> [[RET]]
;
entry:
%ret = call <4 x half> @llvm.copysign.v4f16(<4 x half> splat(half 0xHBC00), <4 x half> %a)
ret <4 x half> %ret
}

; TODO: Support constant folding of fabs

define <4 x half> @copysign_vec4(<4 x half> %a) {
; CHECK-LABEL: @copysign_vec4(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[RET:%.*]] = call <4 x half> @llvm.copysign.v4f16(<4 x half> <half 0xH3C00, half 0xHBC00, half undef, half poison>, <4 x half> [[A:%.*]])
; CHECK-NEXT: ret <4 x half> [[RET]]
;
entry:
%ret = call <4 x half> @llvm.copysign.v4f16(<4 x half> <half 0xH3C00, half 0xHBC00, half undef, half poison>, <4 x half> %a)
ret <4 x half> %ret
}

declare half @llvm.fabs.f16(half)
declare <2 x half> @llvm.fabs.v2f16(<2 x half>)
declare half @llvm.copysign.f16(half, half)
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/Transforms/InstCombine/fcmp.ll
Original file line number Diff line number Diff line change
Expand Up @@ -644,7 +644,7 @@ define <2 x i1> @is_signbit_set_anyzero(<2 x double> %x) {

define i1 @is_signbit_clear(double %x) {
; CHECK-LABEL: @is_signbit_clear(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double -4.200000e+01, double [[X:%.*]])
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 4.200000e+01, double [[X:%.*]])
; CHECK-NEXT: [[R:%.*]] = fcmp ogt double [[S]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -655,7 +655,7 @@ define i1 @is_signbit_clear(double %x) {

define i1 @is_signbit_clear_1(double %x) {
; CHECK-LABEL: @is_signbit_clear_1(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double -4.200000e+01, double [[X:%.*]])
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 4.200000e+01, double [[X:%.*]])
; CHECK-NEXT: [[R:%.*]] = fcmp ugt double [[S]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -666,7 +666,7 @@ define i1 @is_signbit_clear_1(double %x) {

define i1 @is_signbit_clear_2(double %x) {
; CHECK-LABEL: @is_signbit_clear_2(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double -4.200000e+01, double [[X:%.*]])
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 4.200000e+01, double [[X:%.*]])
; CHECK-NEXT: [[R:%.*]] = fcmp oge double [[S]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -677,7 +677,7 @@ define i1 @is_signbit_clear_2(double %x) {

define i1 @is_signbit_clear_3(double %x) {
; CHECK-LABEL: @is_signbit_clear_3(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double -4.200000e+01, double [[X:%.*]])
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 4.200000e+01, double [[X:%.*]])
; CHECK-NEXT: [[R:%.*]] = fcmp uge double [[S]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
Expand Down Expand Up @@ -705,7 +705,7 @@ define i1 @is_signbit_set_extra_use(double %x, ptr %p) {

define i1 @is_signbit_clear_nonzero(double %x) {
; CHECK-LABEL: @is_signbit_clear_nonzero(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double -4.200000e+01, double [[X:%.*]])
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 4.200000e+01, double [[X:%.*]])
; CHECK-NEXT: [[R:%.*]] = fcmp ogt double [[S]], 1.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
Expand Down