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[AMDGPU][NFC] Test clean up #85922

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Mar 20, 2024
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[AMDGPU][NFC] Test clean up #85922

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15 changes: 14 additions & 1 deletion llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@
; RUN: llc -march=amdgcn -mcpu=gfx940 < %s | FileCheck --check-prefixes=GCN %s

; TODO: Add global-isel when it can support bf16

define amdgpu_ps float @v_test_cvt_bf16_f32_v(bfloat %v) {
; GCN-LABEL: v_test_cvt_bf16_f32_v:
; GCN: ; %bb.0:
Expand All @@ -10,6 +11,7 @@ define amdgpu_ps float @v_test_cvt_bf16_f32_v(bfloat %v) {
%cvt = fpext bfloat %v to float
ret float %cvt
}

define amdgpu_ps float @v_test_cvt_bf16_f32_s(bfloat inreg %v) {
; GCN-LABEL: v_test_cvt_bf16_f32_s:
; GCN: ; %bb.0:
Expand All @@ -19,6 +21,7 @@ define amdgpu_ps float @v_test_cvt_bf16_f32_s(bfloat inreg %v) {
%cvt = fpext bfloat %v to float
ret float %cvt
}

define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_v(<2 x float> %src) {
; GCN-LABEL: v_test_cvt_v2f32_v2bf16_v:
; GCN: ; %bb.0:
Expand All @@ -42,6 +45,7 @@ define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_v(<2 x float> %src) {
%cast = bitcast <2 x bfloat> %res to float
ret float %cast
}

define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_s(<2 x float> inreg %src) {
; GCN-LABEL: v_test_cvt_v2f32_v2bf16_s:
; GCN: ; %bb.0:
Expand All @@ -66,6 +70,7 @@ define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_s(<2 x float> inreg %src) {
%cast = bitcast <2 x bfloat> %res to float
ret float %cast
}

define amdgpu_ps float @v_test_cvt_f32_bf16_v(float %src) {
; GCN-LABEL: v_test_cvt_f32_bf16_v:
; GCN: ; %bb.0:
Expand All @@ -82,6 +87,7 @@ define amdgpu_ps float @v_test_cvt_f32_bf16_v(float %src) {
%ext = fpext bfloat %trunc to float
ret float %ext
}

define amdgpu_ps float @v_test_cvt_v2f64_v2bf16_v(<2 x double> %src) {
; GCN-LABEL: v_test_cvt_v2f64_v2bf16_v:
; GCN: ; %bb.0:
Expand Down Expand Up @@ -128,6 +134,7 @@ define amdgpu_ps float @v_test_cvt_v2f64_v2bf16_v(<2 x double> %src) {
%cast = bitcast <2 x bfloat> %res to float
ret float %cast
}

define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16(float %a, float %b) {
; GCN-LABEL: fptrunc_f32_f32_to_v2bf16:
; GCN: ; %bb.0: ; %entry
Expand Down Expand Up @@ -155,6 +162,7 @@ entry:
%ret = bitcast <2 x bfloat> %v2.2 to float
ret float %ret
}

define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16_mods(float %a, float %b) {
; GCN-LABEL: fptrunc_f32_f32_to_v2bf16_mods:
; GCN: ; %bb.0: ; %entry
Expand Down Expand Up @@ -186,6 +194,7 @@ entry:
%ret = bitcast <2 x bfloat> %v2.2 to float
ret float %ret
}

define amdgpu_ps void @fptrunc_f32_to_bf16(float %a, ptr %out) {
; GCN-LABEL: fptrunc_f32_to_bf16:
; GCN: ; %bb.0: ; %entry
Expand All @@ -205,6 +214,7 @@ entry:
store bfloat %a.cvt, ptr %out
ret void
}

define amdgpu_ps void @fptrunc_f32_to_bf16_abs(float %a, ptr %out) {
; GCN-LABEL: fptrunc_f32_to_bf16_abs:
; GCN: ; %bb.0: ; %entry
Expand All @@ -226,6 +236,7 @@ entry:
store bfloat %a.cvt, ptr %out
ret void
}

define amdgpu_ps void @fptrunc_f32_to_bf16_neg(float %a, ptr %out) {
; GCN-LABEL: fptrunc_f32_to_bf16_neg:
; GCN: ; %bb.0: ; %entry
Expand All @@ -247,6 +258,7 @@ entry:
store bfloat %a.cvt, ptr %out
ret void
}

define amdgpu_ps void @fptrunc_f64_to_bf16(double %a, ptr %out) {
; GCN-LABEL: fptrunc_f64_to_bf16:
; GCN: ; %bb.0: ; %entry
Expand Down Expand Up @@ -276,6 +288,7 @@ entry:
store bfloat %a.cvt, ptr %out
ret void
}

define amdgpu_ps void @fptrunc_f64_to_bf16_neg(double %a, ptr %out) {
; GCN-LABEL: fptrunc_f64_to_bf16_neg:
; GCN: ; %bb.0: ; %entry
Expand Down Expand Up @@ -307,6 +320,7 @@ entry:
store bfloat %a.cvt, ptr %out
ret void
}

define amdgpu_ps void @fptrunc_f64_to_bf16_abs(double %a, ptr %out) {
; GCN-LABEL: fptrunc_f64_to_bf16_abs:
; GCN: ; %bb.0: ; %entry
Expand Down Expand Up @@ -341,4 +355,3 @@ entry:

declare float @llvm.fabs.f32(float)
declare double @llvm.fabs.f64(double)