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[AMDGPU] Handle non-register operands for S_SUB/ADD_U64_PSEUDO #86104

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Merged
merged 6 commits into from
Mar 25, 2024
Merged

[AMDGPU] Handle non-register operands for S_SUB/ADD_U64_PSEUDO #86104

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853c39d
[AMDGPU] Handle non-register operands for S_SUB/ADD_U64_PSEUDO
Pierre-vh Mar 21, 2024
cb5c8ad
clang-format
Pierre-vh Mar 21, 2024
693b2ac
ignore clang-format
Pierre-vh Mar 21, 2024
e469b94
drop comments
Pierre-vh Mar 21, 2024
ef6356c
add test
Pierre-vh Mar 22, 2024
cb1dbf8
remove verify
Pierre-vh Mar 25, 2024
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4858,8 +4858,8 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
if (Subtarget->hasScalarAddSub64()) {
unsigned Opc = IsAdd ? AMDGPU::S_ADD_U64 : AMDGPU::S_SUB_U64;
BuildMI(*BB, MI, DL, TII->get(Opc), Dest.getReg())
.addReg(Src0.getReg())
.addReg(Src1.getReg());
.add(Src0)
.add(Src1);
} else {
const SIRegisterInfo *TRI = ST.getRegisterInfo();
const TargetRegisterClass *BoolRC = TRI->getBoolRC();
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68 changes: 68 additions & 0 deletions llvm/test/CodeGen/AMDGPU/add_sub_u64_pseudos.mir
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@@ -0,0 +1,68 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=finalize-isel -o - %s | FileCheck -check-prefix=GFX11 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=finalize-isel -o - %s | FileCheck -check-prefix=GFX12 %s

---
name: reg_ops
tracksRegLiveness: true
body: |
bb.0:
; GFX11-LABEL: name: reg_ops
; GFX11: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GFX11-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[DEF1]].sub0
; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[DEF1]].sub1
; GFX11-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY2]], implicit-def $scc
; GFX11-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY1]], [[COPY3]], implicit-def $scc, implicit $scc
; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
;
; GFX12-LABEL: name: reg_ops
; GFX12: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GFX12-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GFX12-NEXT: [[S_ADD_U64_:%[0-9]+]]:sreg_64 = S_ADD_U64 [[DEF]], [[DEF1]]
%0:sreg_64 = IMPLICIT_DEF
%1:sreg_64 = IMPLICIT_DEF
%2:sreg_64 = S_ADD_U64_PSEUDO %0, %1, implicit-def $scc
...

---
name: lhs_imm
tracksRegLiveness: true
body: |
bb.0:
; GFX11-LABEL: name: lhs_imm
; GFX11: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
; GFX11-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 6565, [[COPY]], implicit-def $scc
; GFX11-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 0, [[COPY1]], implicit-def $scc, implicit $scc
; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
;
; GFX12-LABEL: name: lhs_imm
; GFX12: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GFX12-NEXT: [[S_ADD_U64_:%[0-9]+]]:sreg_64 = S_ADD_U64 6565, [[DEF]]
%0:sreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_ADD_U64_PSEUDO 6565, %0, implicit-def $scc
...

---
name: rhs_imm
tracksRegLiveness: true
body: |
bb.0:
; GFX11-LABEL: name: rhs_imm
; GFX11: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
; GFX11-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], 6565, implicit-def $scc
; GFX11-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY1]], 0, implicit-def $scc, implicit $scc
; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
;
; GFX12-LABEL: name: rhs_imm
; GFX12: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GFX12-NEXT: [[S_ADD_U64_:%[0-9]+]]:sreg_64 = S_ADD_U64 [[DEF]], 6565
%0:sreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_ADD_U64_PSEUDO %0, 6565, implicit-def $scc
...