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[LLD][RISCV] Add relaxation for absolute int12 Hi20Lo12 #86124

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Merged
merged 3 commits into from
Mar 21, 2025
Merged

[LLD][RISCV] Add relaxation for absolute int12 Hi20Lo12 #86124

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9f64b25
[LLD][RISCV] Add relaxation for absolute int12 Hi20Lo12
preames Mar 20, 2024
e06cef5
Simplify relocate implementation
preames Mar 22, 2024
46e5526
Merge branch 'main' into pr-lld-riscv-relax-absolute-12bit
preames Mar 20, 2025
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38 changes: 37 additions & 1 deletion lld/ELF/Arch/RISCV.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -50,10 +50,12 @@ class RISCV final : public TargetInfo {

} // end anonymous namespace

// These are internal relocation numbers for GP relaxation. They aren't part
// These are internal relocation numbers for GP/X0 relaxation. They aren't part
// of the psABI spec.
#define INTERNAL_R_RISCV_GPREL_I 256
#define INTERNAL_R_RISCV_GPREL_S 257
#define INTERNAL_R_RISCV_X0REL_I 258
#define INTERNAL_R_RISCV_X0REL_S 259

const uint64_t dtpOffset = 0x800;

Expand All @@ -70,6 +72,7 @@ enum Op {
};

enum Reg {
X_X0 = 0,
X_RA = 1,
X_GP = 3,
X_TP = 4,
Expand Down Expand Up @@ -447,6 +450,18 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
return;
}

case INTERNAL_R_RISCV_X0REL_I:
case INTERNAL_R_RISCV_X0REL_S: {
checkInt(ctx, loc, val, 12, rel);
uint32_t insn = (read32le(loc) & ~(31 << 15)) | (X_X0 << 15);
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To call out one possible concern with this patch. If there is an IType or SType instruction whose encoding reserved rs1=x0 (or otherwise gave it distinct behavior) this transform would not be legal. I did a search through the ISA manual and didn't find anything, but that doesn't mean such a special case definitely doesn't exist. In principal such a special case is also possible for GP, but there's a lot more precedent for X0 being special in the encoding (though usually as the value for RD).

if (rel.type == INTERNAL_R_RISCV_X0REL_I)
insn = setLO12_I(insn, val);
else
insn = setLO12_S(insn, val);
write32le(loc, insn);
return;
}

case INTERNAL_R_RISCV_GPREL_I:
case INTERNAL_R_RISCV_GPREL_S: {
Defined *gp = ctx.sym.riscvGlobalPointer;
Expand Down Expand Up @@ -772,6 +787,25 @@ static void relaxTlsLe(Ctx &ctx, const InputSection &sec, size_t i,

static void relaxHi20Lo12(Ctx &ctx, const InputSection &sec, size_t i,
uint64_t loc, Relocation &r, uint32_t &remove) {

// Fold into use of x0+offset
if (isInt<12>(r.sym->getVA(ctx, r.addend))) {
switch (r.type) {
case R_RISCV_HI20:
// Remove lui rd, %hi20(x).
sec.relaxAux->relocTypes[i] = R_RISCV_RELAX;
remove = 4;
break;
case R_RISCV_LO12_I:
sec.relaxAux->relocTypes[i] = INTERNAL_R_RISCV_X0REL_I;
break;
case R_RISCV_LO12_S:
sec.relaxAux->relocTypes[i] = INTERNAL_R_RISCV_X0REL_S;
break;
}
return;
}

const Defined *gp = ctx.sym.riscvGlobalPointer;
if (!gp)
return;
Expand Down Expand Up @@ -974,6 +1008,8 @@ void RISCV::finalizeRelax(int passes) const {
switch (newType) {
case INTERNAL_R_RISCV_GPREL_I:
case INTERNAL_R_RISCV_GPREL_S:
case INTERNAL_R_RISCV_X0REL_I:
case INTERNAL_R_RISCV_X0REL_S:
break;
case R_RISCV_RELAX:
// Used by relaxTlsLe to indicate the relocation is ignored.
Expand Down
23 changes: 20 additions & 3 deletions lld/test/ELF/riscv-relax-hi20-lo12.s
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Expand Up @@ -4,12 +4,12 @@
# RUN: llvm-mc -filetype=obj -triple=riscv32-unknown-elf -mattr=+relax a.s -o rv32.o
# RUN: llvm-mc -filetype=obj -triple=riscv64-unknown-elf -mattr=+relax a.s -o rv64.o

# RUN: ld.lld --relax-gp --undefined=__global_pointer$ rv32.o lds -o rv32
# RUN: ld.lld --relax-gp --undefined=__global_pointer$ rv64.o lds -o rv64
# RUN: ld.lld --relax-gp --undefined=__global_pointer$ --defsym baz=420 rv32.o lds -o rv32
# RUN: ld.lld --relax-gp --undefined=__global_pointer$ --defsym baz=420 rv64.o lds -o rv64
# RUN: llvm-objdump -td -M no-aliases --no-show-raw-insn rv32 | FileCheck %s
# RUN: llvm-objdump -td -M no-aliases --no-show-raw-insn rv64 | FileCheck %s

# CHECK: 00000028 l .text {{0*}}0 a
# CHECK: 00000040 l .text {{0*}}0 a

# CHECK-NOT: lui
# CHECK: addi a0, gp, -0x800
Expand All @@ -23,6 +23,14 @@
# CHECK-NEXT: addi a0, a0, 0x0
# CHECK-NEXT: lw a0, 0x0(a0)
# CHECK-NEXT: sw a0, 0x0(a0)
# CHECK-NOT: lui
# CHECK: addi a0, zero, 0x0
# CHECK-NEXT: lw a0, 0x0(zero)
# CHECK-NEXT: sw a0, 0x0(zero)
# CHECK-NOT: lui
# CHECK: addi a0, zero, 0x1a4
# CHECK-NEXT: lw a0, 0x1a4(zero)
# CHECK-NEXT: sw a0, 0x1a4(zero)
# CHECK-EMPTY:
# CHECK-NEXT: <a>:
# CHECK-NEXT: addi a0, a0, 0x1
Expand All @@ -42,6 +50,14 @@ _start:
addi a0, a0, %lo(norelax)
lw a0, %lo(norelax)(a0)
sw a0, %lo(norelax)(a0)
lui a0, %hi(undefined_weak)
addi a0, a0, %lo(undefined_weak)
lw a0, %lo(undefined_weak)(a0)
sw a0, %lo(undefined_weak)(a0)
lui a0, %hi(baz)
addi a0, a0, %lo(baz)
lw a0, %lo(baz)(a0)
sw a0, %lo(baz)(a0)
a:
addi a0, a0, 1

Expand All @@ -53,6 +69,7 @@ bar:
.byte 0
norelax:
.word 0
.weak undefined_weak

#--- lds
SECTIONS {
Expand Down